참고문헌
- Patti, R.S.;, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs," Proceedings of the IEEE, vol.94, no.6, pp.1214-1224, June 2006. https://doi.org/10.1109/JPROC.2006.873612
- Davis, W.R.; Wilson, J.; Mick, S.; Xu, J.; Hua, H.; Mineo, C.; Sule, A.M.; Steer, M.; Franzon, P.D.;, "Demystifying 3D ICs: the pros and cons of going vertical," Design &Test of Computers, IEEE, vol.22, no.6, pp. 498- 510, Nov.-Dec. 2005. https://doi.org/10.1109/MDT.2005.136
- Philip Garrou; Christopher Bower; and Peter Ramm;, "Handbook of 3D Integration: Technology and Application of 3D Integrated Circuits Volume 1 & 2," published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim, 2008, ISBN: 978-3-527-32034-9.
- Lee, H.-H.S.; Chakrabarty, K.;, "Test Challenges for 3D Integrated Circuits," Design &Test of Computers, IEEE, vol.26, no.5, pp.26-35, Sept.-Oct. 2009.
- Marinissen, E.J.; Zorian, Y.;, "Testing 3D chips containing through-silicon vias," Test Conference, 2009. ITC 2009. International, vol., no., pp.1-11, 1-6 Nov. 2009.
- Marinissen, E.J.;, "Testing TSV-based three-dimensional stacked ICs," Design, Automation &Test in Europe Conference &Exhibition (DATE), 2010, vol., no., pp.1689-1694, 8-12 March 2010.
- Marinissen, E.J.; Verbree, J.; Konijnenburg, M.;, "A structured and scalable test access architecture for TSV-based 3D stacked ICs," VLSI Test Symposium (VTS), 2010 28th, vol., no., pp.269-274, 19-22 April 2010.
- Ang-Chih Hsieh; TingTing Hwang; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Li, H.-C.;, "TSV redundancy: Architecture and design issues in 3D IC," Design, Automation &Test in Europe Conference &Exhibition (DATE), 2010, vol., no., pp.166-171, 8-12 March 2010.
- Uksong Kang; Hoe-Ju Chung; Seongmoo Heo; Soon-Hong Ahn; Hoon Lee; Soo-Ho Cha; Jaesung Ahn; DukMin Kwon; Jin Ho Kim; Jae-Wook Lee; Han-Sung Joo; Woo-Seop Kim; Hyun-Kyung Kim; Eun-Mi Lee; So-Ra Kim; Keum-Hee Ma; Dong-Hyun Jang; Nam-Seog Kim; Man-Sik Choi; Sae-Jang Oh; Jung-Bae Lee; Tae-Kyung Jung; Jei-Hwan Yoo; Changhyun Kim;, "8Gb 3D DDR3 DRAM using through-silicon-via technology," Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, vol., no., pp.130-131,131a, 8-12 Feb. 2009.
- Po-Yuan Chen; Cheng-Wen Wu; Ding-Ming Kwai;, "On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification," Asian Test Symposium, 2009. ATS '09., vol., no., pp.450-455, 23-26 Nov. 2009.