JSTS:Journal of Semiconductor Technology and Science

  • 제11권3호
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  • Pages.198-206
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  • 2011
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Programmable Compensation Circuit for System-on-Chip Application

  • Choi, Woo-Chang (MEMS/NANO Fabrication Center, Busan Techno-Park) ;
  • Ryu, Jee-Youl (Information and Communications Engineering, Pukyong National University)
  • 투고 : 2011.05.25
  • 발행 : 2011.09.30
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초록

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

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참고문헌

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피인용 문헌

  1. A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique vol.16, pp.4, 2016, https://doi.org/10.5573/JSTS.2016.16.4.443
  2. An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications vol.16, pp.5, 2016, https://doi.org/10.5573/JSTS.2016.16.5.595