Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Threshold and Flat Band Voltage Modeling and Device design Guideline in Nanowire Junctionless Transistors

나노와이어 junctionless 트랜지스터의 문턱전압 및 평탄전압 모델링과 소자설계 가이드라인

  • Kim, Jin-Young (Dept. of Electronics Engineering, University of Incheon) ;
  • Yu, Chong-Gun (Dept. of Electronics Engineering, University of Incheon) ;
  • Park, Jong-Tae (Dept. of Electronics Engineering, University of Incheon)
  • Received : 2011.10.11
  • Published : 2011.12.25
Download PDF
⟨ Previous Next ⟩

Abstract

In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

본 연구에서는 나노와이어 junctionless 트랜지스터의 문턱전압과 평탄전압을 위한 해석학적 모델링을 제시하였고 3차원 소자 시뮬레이션으로 검증하였다. 그리고 junctionless 트랜지스터의 소자설계 가이드라인을 설정하는 방법과 그 예를 제시하였다. 제시한 문턱전압과 평탄전압 모델은 3차원 시뮬레이션 결과와 잘 일치하였다. 나노와이어 반경과 게이트 산화층 두께가 클수록 또 채널 불순물 농도가 높을수록 문턱전압과 평탄전압은 감소하였다. 게이트 일함수와 원하는 구동전류/누설전류 비가 주어지면 나노와이어 반경, 게이트 산화층 두께, 채널 불순물 농도에 따른 junctionless 트랜지스터의 소자설계 가이드라인을 설정하였다. 나노와이어 반경이 작을수록 산화층의 두께가 얇을수록 채널 불순물 농도가 큰 소자를 설계할 수 있음을 알 수 있었다.

Keywords

References

  1. Jong Tae Park, and J. P. Colinge, "Multiple gate SOI MOSFETs :Device design guidelines," IEEE Trans. Electron Device, vol. 49, no,12, pp. 2222-2228, 2002. https://doi.org/10.1109/TED.2002.805634
  2. J. P. Colinge, "Multiple-gate SOI MOSFETs," Solid-state Electronics, vol.48, no.6, pp.897-905, 2004. https://doi.org/10.1016/j.sse.2003.12.020
  3. R. Yan, D. Lynch, T. Cayron, D. Lederer, A Afzalian, C. W. Lee, and J. P. Colinge, "Sensitivity of trigate MOSFETs to random dopant incuced threshold voltage fluctuations," Solid-state Electronics, vol. 52, no.12, pp. 1872-1876, 2008. https://doi.org/10.1016/j.sse.2008.06.061
  4. D. J. frank, R. H. Dennard, E. Novak, P. M. Solomon, Y. Taur, and H. S. P. Wong, "Device scaling limits of Si MOSFET and their application dependence," Proc. IEEE, vol. 89, no. 3, pp. 259-288, 2001. https://doi.org/10.1109/5.915374
  5. S. H. Jain, "Low resistance, low leakage ultrashallow $p^+$ junction formation using millisecond flash anneals," IEEE Trans Electron Devices, vol. 52, no. 7, pp. 1610-1615, 2003.
  6. N. J. Quitoriano, and T. I. Kamins, "Integratable nanowire transistors," Nano letters, vol. 8, no. 12, pp. 4410-4414, 2008. https://doi.org/10.1021/nl802292h
  7. P. Yang, R. Yan, and M. Fardy, "Semiconductor nanowire: what's next?," Nano Letters, vol. 11, no. 10, pp. 1529-1536, 2010.
  8. M. Masahara, K .Endo, Y. Liu, T. Matsukawa, S. Ouchi, K. Ishii, E. Sugimata, E. Suzuki, "Demostration and analysis of accumulation-mode double-gate metal oxide semiconductor field effect transistor," Jpn J. Appl. Phys., vol. 45, no. 4b, pp. 079-3083, 2006. https://doi.org/10.1143/JJAP.45.3079
  9. J. P. Colinge, C. W. Lee, A. Afzalian, N. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junction," Nature Nanotechnology, vol. 5, no. 3, pp. 225-229, 2010. https://doi.org/10.1038/nnano.2010.15
  10. C. W. Lee, A. N. Nazarov, I. Ferain, N. Dehdashti, R. Yan, P. Razavi, R. Yu, Rodrigo T. Doria, J. P. Colinge, "Low subthreshold slope in junctionless multiplegate transistors," Appl. Phys. Lett. vol. 96, pp. 102106, 2010. https://doi.org/10.1063/1.3358131
  11. J. P. Raskin, J. P. Colinge, I. Ferain, A. Kranti, C. W. Lee, N. Dehdashti, R. Yan, P. razavi, R. Yu, "Mobility improvement in nanowire junctionless transistors by uniaxial strain," Appl. Phys. lett., vol. 97, pp. 042114, 2010. https://doi.org/10.1063/1.3474608
  12. C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, J. P. Colinge, "Performance estimation of junctionless multiple gate transistors," Solid-state Electronics, vol. 54, no. 2, pp. 97-103, 2010. https://doi.org/10.1016/j.sse.2009.12.003
  13. R. D. Trevisoli, M. A. Pavanello, R. T. Doria, M. de Souza, C. W. Lee, I ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti, and J. P. Colinge, "Analytical model for the threshold voltage of junctionless nanowire transistors," Proceeding of EUROSOI Workshop pp. 67-68, 2011.
  14. N. lifshitz, "Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon," IEEE Trans Electron Devices vol. 325, no. 3, pp. 617-621, 1985.