대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

병렬처리 기반의 H.264/AVC 인코더를 위한 저 메모리 대역폭 움직임 예측 코어설계

A Low Memory Bandwidth Motion Estimation Core for H.264/AVC Encoder Based on Parallel Current MB Processing

  • 김시혜 (경북대학교 전자전기컴퓨터학부) ;
  • 최준림 (경북대학교 전자전기컴퓨터학부)
  • Kim, Shi-Hye (Kyungpook National University, School of Electrical Engineering and Computer Science) ;
  • Choi, Jun-Rim (Kyungpook National University, School of Electrical Engineering and Computer Science)
  • 투고 : 2010.11.15
  • 발행 : 2011.02.25
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초록

본 논문에서는 H.264/AVC 인코더를 위한 하드웨어 지향 알고리즘의 정화소 및 부화소 움직임 예측 코어를 제안한다. 정화소 움직임 엔진의 경우 참조블록은 병렬 처리 내의 연속된 현재 블록들에 공유되어 데이터 재사용율을 높이고 오프칩 대역폭을 줄인다. 부화소 움직임 엔진의 경우 두 단계의 순차적 보간 신호 생성 대신 불필요한 후보 위치들 대신 1/2과 1/4 화소정밀도 신호를 병렬 기법으로 생성하여 처리량을 두배로 높인다. 또한 제안하는 H.264 움직임 예측 코어는 Chartered $0.18{\mu}m$ CMOS 1P5M 공정의 MPW(Multi-Project Wafer)를 통해 칩으로 제작되었으며 높은 처리량으로 HDTV 720p 30fps를 실시간 지원한다.

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

키워드

참고문헌

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