The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
권호 표지
DOI QR코드

DOI QR Code

Design of Degree-Computationless Modified Euclidean Algorithm using Polynomial Expression

다항식 표현을 이용한 DCME 알고리즘 설계

  • 강성진 (한국기술교육대학교 전기전자통신공학부) ;
  • 김남용 (강원대학교 공학대학 전자정보통신공학부)
  • Received : 2011.08.17
  • Accepted : 2011.10.05
  • Published : 2011.10.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

본 논문에서는 고속 RS(Reed-Solomon) 복호기의 KES(Key Equation Solver) 블록 구현에 ME(Modified Euclidean) 알고리즘을 효율적으로 설계할 수 있는 구조를 제안하고 구현하였다. 제안된 구조에서는 각 PE(Processing Element) 블록을 제어하기 위해 새로운 상대변수를 정의하고 다항식으로 표현함으로써, 입출력 신호가 간단해지고, 차수계산회로가 필요 없기 때문에 회로의 복잡도를 줄일 수 있다. 또한, PE 회로가 오류 정정 능력 t와 무관하기 때문에, t가 증가함에 따라 KES 블록의 하드웨어 복잡도가 선형적으로 증가하는 장점을 가진다. 제안된 구조와 기존의 구조를 비교하기 위해, RS(255,239,8) 복호기에 대한 KES 블록을 구현하고, 0.13um CMOS cell library를 이용하여 합성하였다. 실험 결과로부터, 제안된 구조를 이용하여 적은 gate count로 고속 RS 복호기 구현이 가능함을 알 수 있다.

Keywords

References

  1. S. B. Wicker, Error Control Systems for Digital Communication and Storage, Englewood Cliffs, NJ, Prentice-Hall, 1995.
  2. H. Shao, T. Truong, L. Deutsch, J. Yuen, I. Reed, "A VLSI design of a Pipeline Reed-Solomon Decoder," IEEE Trans. on Computers, Vol.c-34, No.5, pp.393-403, May 1985. https://doi.org/10.1109/TC.1985.1676579
  3. L. Song, M. Yu, M. Shaffer, "10- and 40-Gb/s Forward Error Correction Devices for Optical Communications," IEEE Journal of Soild-State Circuits, Vol.37, No.11, pp.1565-1573, Nov. 2002. https://doi.org/10.1109/JSSC.2002.803931
  4. Hanho Lee, "High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder," IEEE Trans. on VLSI Systems, Vol.11, No.2, pp.288-294, April 2003. https://doi.org/10.1109/TVLSI.2003.810782
  5. S. Lee, H. Lee, "A High-Speed Pipelined Degree- Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," IEICE Trans. Fundamentals, Vol.E91-A, No.3, pp.830-835, March, 2008. https://doi.org/10.1093/ietfec/e91-a.3.830
  6. J. H. Baek and M. H. SunWoo, "New degree computationless modified Euclid's algorithm and architecture for Reed-Solomon decoder", IEEE Trans. Very Large Integr. (VLSI) Syst., Vol.14, No.8, pp.915-920, Aug. 2006. https://doi.org/10.1109/TVLSI.2006.878484
  7. J. H. Baek and M. H. SunWoo, "Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoders," Electronics Letters, Vol.43, No.3, pp.175-176, Feb., 2007. https://doi.org/10.1049/el:20073718
  8. 강성진, 김한종 "UWB 시스템을 위한 RS(23,17) 복호기 최적 설계," 한국통신학회논문지, Vol.33, No.8, pp.821-828, Aug., 2008.
  9. J. Proakis, M. Salehi, Digital Communications, McGraw-Hill, 5th ed., 2008