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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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High Repair Efficiency BIRA Algorithm with a Line Fault Scheme

  • Han, Tae-Woo (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Jeong, Woo-Sik (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Park, Young-Kyu (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
  • Received : 2010.03.24
  • Accepted : 2010.06.03
  • Published : 2010.08.30
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Abstract

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

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References

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