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A 50-mA 1-nF Low-Voltage Low-Dropout Voltage Regulator for SoC Applications

  • Giustolisi, Gianluca (Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Universita degli Studi di Catania) ;
  • Palumbo, Gaetano (Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Universita degli Studi di Catania) ;
  • Spitale, Ester (Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Universita degli Studi di Catania)
  • Received : 2010.09.29
  • Accepted : 2010.01.22
  • Published : 2010.08.30
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Abstract

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.

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References

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