References
- S.Mitra, N.R.Saxena, and E.J.McCluskey,"Efficient Design diversity Estimation for Combinational Circuits," IEEE Trans. on Computers, pp.1483-1492, Vol.53, No.11, Nov. 2004. https://doi.org/10.1109/TC.2004.95
- D.Lee,A.A. Gaffar, O.Mencer, and W.Luk,"Optimization Hardware Function Evaluation," IEEE Trans. Comput., vol.54, No.12, pp.1520-1531, Dec., 2005. https://doi.org/10.1109/TC.2005.201
- D.Lee, A.Abuda Gaffar, O.Mencer, and W.Luk,"Optimizing hardware function evaluation," IEEE Trans. Comput. pp.1520-1531, vol.54, Dec. 2005. https://doi.org/10.1109/TC.2005.201
- R. sastry and Ranganathan,"A VLSI Architecture for Approximate Tree Matching," IEEE Trans. Comput., vol.47, no.3, pp.346-352, Mar. 1988.
- K.J.Lin, C.W.Kuo and C.S.Lin,"Synthesis of hazard-free asynchronous circuits based on characteristic Graph," IEEE Trans. Copmut., vol.46, no.11, pp. 1246-1263, Nov. 1987.
- I. Pomeranz and S.M.reddy,"Test Generation for multiple State- Table Faults in Finite-State Machines," IEEE Trans. Comput., vol.45, no.7, pp.783-794,Jul. 1987.
- David Green, Modern Logic Design, Addison-Wesley Publishing Company, 1986.
- Thurman A. Irving, Sajjan G.Shiva and H. Troy Nagle,"Flip-Flops for Multiple-Valued logic," IEEE Trans Compt.,vol.c-25, pp.237-246,Mar.1976. https://doi.org/10.1109/TC.1976.5009250
- Anthony S. Wojiok and Kwang-Ya Fang, "On the design of threevalued asynchronous modules," IEEE Trans. Compt., vol. C-29,pp.889-898, Oct.1980. https://doi.org/10.1109/TC.1980.1675472
- L.P. Maguire, T.M.McGinnity and L.J. McDaid,"From a Fuzzy Flip-Flop to a MVL Flip-Flop," The 29th IEEE ISMVL, Freiburgim Breisgau, Germany, pp.294-299, 20-22 May, 1999.
- R. Drechsler, M. Keim and B. Becker,"Fault Simulation in Sequential Multi-valued Logic networks," The 27th IEEE ismvl , NOVA SCOTIA, CANADA, .pp.145-150, 28-30 May, 1997.