The Journal of Korean Institute of Electromagnetic Engineering and Science (한국전자파학회논문지)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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Design of Variable Gain Low Noise Amplifier with Memory Effects Feedback for 5.2 GHz Band

5.2 GHz 대역에서 동작하는 기억 기능 특성을 갖는 궤환 회로를 이용한 변환 이득 저잡음 증폭기 설계

  • Lee, Won-Tae (Department of Computer and Radio Communication Engineering, Korea University) ;
  • Jeong, Ji-Chai (Department of Computer and Radio Communication Engineering, Korea University)
  • 이원태 (고려대학교 전파통신공학과) ;
  • 정지채 (고려대학교 전파통신공학과)
  • Published : 2010.01.31
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Abstract

This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

본 논문에서는 5.2 GHz에서 입력 신호의 크기에 따라 효율적으로 동작하는 저잡음 증폭기를 0.18 um CMOS 공정을 이용하여 설계하였다. 제안된 회로는 궤환 회로와 2단 저잡음 증폭기로 구성되어 있으며, 궤환 회로의 경우 7개의 함수 블록으로 구성되어 있다. 본 논문에서는 변화되는 신호 전압을 감지하는 것과 이전 상태를 기억하는 저장 회로에 초점을 두어 불필요한 전력 소비를 제거하였다. 기억 기능 특성을 갖는 궤환 회로의 출력값을 이용하여 통제되는 저잡음 증폭기는 11.39 dB에서 22.74 dB까지 변하며, 최고 이득 모드일 때 잡음 지수가 최적화 되도록 설계되었다. 변환 저잡음 증폭기는 1.8 V의 공급 전압에 대해서 5.68~6.75 mW를 소비한다.

Keywords

References

  1. C. Cha, S. Lee, "A 5.2-GHz LNA in 0.35 um CMOS utilizing inter-stage series resonance and optimizing the substrate resistance", IEEE Journal of Solid-State Circuits, vol. 38, pp. 669-672, Apr. 2003. https://doi.org/10.1109/JSSC.2003.809523
  2. A. Vallese, A. Neviani, "Analysis and design of an integrated notch filter for the rejection of interence in UWB system", IEEE Journal of Solid-State Circuits, vol. 44, pp. 331-343, Feb. 2009. https://doi.org/10.1109/JSSC.2008.2010984
  3. K. Han, K. Lee, "Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2 GHz low noise amplifier", IEEE Journal of Solid-State Circuits, vol. 40, pp. 726-735, Mar. 2005. https://doi.org/10.1109/JSSC.2005.843637
  4. R. Barker, CMOS Circuit Design Layout Simulation, IEEE Pressseries on Microelectronic System 2nd Edition, pp. 985-995, May 2005.
  5. D. K. Shaeffer, T. H. Lee, "A 1.5 V, 1.5 GHz CMOS low noise amplifier", IEEE Journal of Solid-State Circuits, vol. 32, pp. 745-759, May 1997. https://doi.org/10.1109/4.568846
  6. T. Kien, S. G. Lee, "CMOS low noise amplifier design optimization technique", IEEE Trans. Microwave Theory and Techniques, vol. 52, no. 5, pp. 1433-1442, May 2004. https://doi.org/10.1109/TMTT.2004.827014
  7. H. O. Elwan, M. lsmail, "Digitally programmable decibel-linear CMOS VGA for low-power mixed signal applications", IEEE Trans. Microwave Theory and Techniques, vol. 47, no. 5, pp. 388-398, May 2000. https://doi.org/10.1109/82.842107
  8. F. Piazza, P. Tsivis, "A 2 mA/3 V 71 MHz IF amplifier in 0.4 um CMOS programmable over range", ISSCC, session 5, pp. 78-79, Feb. 2009.
  9. W. Song, C. Cho, "High frequency/high dynamic range CMOS VGA", Electrical Letters, vol. 35, pp. 1096-1098, Jun. 2000.
  10. A. Bevilacqua, A. M. Niknejad, "An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless reciver", ISSCC, session 21, pp. 382-533, Dec. 2004.
  11. J. Hu, L. Ragan, "A fully integrated variable gain 5.75 GHz LNA with on chip active balun for WLAN", IEEE Trans. Microwave Theory and Techniques, vol. 55, no. 7, pp. 388-398, Aug. 2008.