JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

  • Cho, Seong-Jae (Electrical Engineering Department, Stanford University) ;
  • O'uchi, Shinichi (Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)) ;
  • Endo, Kazuhiko (Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)) ;
  • Kim, Sang-Wan (School of Electrical Engineering and Computer Science, and Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Son, Young-Hwan (School of Electrical Engineering and Computer Science, and Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Kang, In-Man (School of Electronics Engineering, Kyungpook National University) ;
  • Masahara, Meishoku (Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)) ;
  • Harris, James S.Jr (Electrical Engineering Department, Stanford University) ;
  • Park, Byung-Gook (School of Electrical Engineering and Computer Science, Seoul National University)
  • Received : 2010.11.04
  • Published : 2010.12.31
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Abstract

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

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