대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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R2SDF FFT의 메모리 감소를 위한 회전인자 인덱스 생성방법

Twiddle Factor Index Generate Method for Memory Reduction in R2SDF FFT

  • 양승원 (전북대학교 전자정보공학부) ;
  • 김용은 (전북대학교 전자정보공학부) ;
  • 이종열 (전북대학교 전자정보공학부)
  • Yang, Seung-Won (Division of Electronic & Information Engineering Chonbuk National University) ;
  • Kim, Yong-Eun (Division of Electronic & Information Engineering Chonbuk National University) ;
  • Lee, Jong-Yeol (Division of Electronic & Information Engineering Chonbuk National University)
  • 발행 : 2009.05.25
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초록

FFT(Fast Fourier Transform) 프로세서는 OFDM(Orthogonal Frequency Division Multiplexing) 시스템에서 사용된다. 근래에는 광대역과 이동성에 대한 요구가 높아짐에 따라 큰 포인트를 가지는 FFT 프로세서의 연구가 필요하다. FFT 포인트 수가 증가할수록 회전인자가 저장된 메모리가 차지하는 면적은 증가한다. 본 논문에서는 Radix-2, $2^2,\;2^3,\;2^4$ 알고리즘의 회전인자 인덱스 생성 방법을 제안한다. 제안한 회전인자 인덱스 생성기(Twiddle Factor Index Generator : TFIG)는 간단하게 카운터와 양수곱셈기로만 구성된다. 각각의 R2SDF(Radix-2 Single-Path Delay Feedback), $R2^2SDF,\;R2^3SDF,\;R2^4SDF$ 1024포인트 FFT 프로세서에 ROM 크기를 1/8N로 줄인 회전인자 계수 생성기(Twiddle Factor Coefficient Generator : TFCG)를 설계하여 제안한 알고리즘을 검증하였다. $R2^4SDF$의 TFCG 경우 면적, 전력에서 각 57.9%, 57.5%정도의 이득을 얻었다.

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

키워드

참고문헌

  1. E. H. Wold, A.M. Despain, 'Pipeline and parallel-pipeline FFT processors for VLSI implementation'. IEEE Trans. Comput, C-33(5): 414-426, May 1984 https://doi.org/10.1109/TC.1984.1676458
  2. Shousheng He, Torkelson, M, 'Designing pipeline FFT processor for OFDM (de)modulation' , Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on, pp. 257 - 262, 29 Sept.-2 Oct. 1998 https://doi.org/10.1109/ISSSE.1998.738077
  3. ].y. Oh, M.S. Lim, 'Area and power efficient pipeline FFT algorithm', Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on, pp. 520-525, 2-4 Nov. 2005 https://doi.org/10.1109/SIPS.2005.1579923
  4. S. Y. Lee, C. C. Chen, C. C. Lee, C. J. Cheng, 'A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a sirnple memory control scheme', Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp. -160, Sept. 2006 https://doi.org/10.1109/ISCAS.2006.1692546
  5. 민종균， 조중휘， 'DVB용. 2K/8K FFT의. Stratix EP1S25F672C6 FPGA 구현', 대한전자공학회 논문지 제44권 SD 제 8호 pp. 60-64, 2007
  6. Huirae Cho, Myung-Soon Kim, Duk-Bai Kirn and Jin-Up Kim, 'R22 SDF FFT Implementation with Coefficient Memory Reduction Scheme', Vehicular Technology Conference 2006 pp. 1-4, Sept. 2006 https://doi.org/10.1109/VTCF.2006.321