Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Pattern Mapping Method for Low Power BIST

저전력 BIST를 위한 패턴 사상(寫像) 기법에 관한 연구

  • Kim, You-Bean (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Jang, Jae-Won (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Son, Hyun-Uk (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
  • 김유빈 (연세대학교 전기전자공학과) ;
  • 장재원 (연세대학교 전기전자공학과) ;
  • 손현욱 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2009.05.25
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Abstract

This paper proposes an effective low power BIST architecture using the pattern mapping method for 100% fault coverage and the transition freezing method for making high correlative low power patterns. When frozen patterns are applied to a circuit, it begins to find a great number of faults at first. However, patterns have limitations of achieving 100% fault coverage due to random pattern resistant faults. In this paper, those faults are covered by the pattern mapping method using the patterns generated by an ATPG and the useless patterns among frozen patterns. Throughout the scheme, we have reduced an amount of applied patterns and test time compared with the transition freezing method, which leads to low power dissipation.

본 논문은 유사랜덤 방식의 BIST를 기반으로 하여 스캔 shifting시의 transition을 획기적으로 줄여 주었던 transition freezing 기법과 새롭게 제안하는 고장검출율 100%를 위한 pattern mapping 기법을 결합한 효과적인 저전력 BIST구조에 대해 제안한다. Transition freezing 기법으로 생성된 고연관의 저전력 패턴은 패턴 인가 초기에는 많은 수의 고장을 검출해 내지만, 패턴의 수가 점점 늘어날수록 랜덤 저항 고장의 증가로 인해 추가적인 고장 검출에는 한계가 있었다. 이러한 비검출 고장에 대해 ATPG를 통한 테스트 패턴을 생성하여, 고장을 검출하지 못하는 frozen pattern과 mapping을 함으로써 기 생성된 패턴을 재활용하여 인가되는 패턴의 수와 테스트 시간을 줄임으로써 전력 소모량을 줄일 수 있었다.

Keywords

References

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