References
- S. Wang, 'Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST' , Proc. IEEE International Test Conference (ITC) , 2002, pp. 834-843 https://doi.org/10.1109/TEST.2002.1041837
- Xiaodong Zhang and Kaushik Roy, 'Peak Power Reduction in Low Power BIST', Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), 2000, pp. 425-432 https://doi.org/10.1109/ISQED.2000.838911
- Debjyoti Ghosh, Swarup Bhunia, and Kaushik Roy, 'A Techniqueto Reduce Power and Test Application Time in BIST' , Proc. IEEE International On-Line Testing Symposium (IOLTS), 2004, pp. 182-183
- Mohammed EIShoukry, c.P. Ravikumar, and Mohammad Te-hranipoor, 'Partial Gating Optimization for Power Reduction During Test Application', Proc. of IEEE Asian Test Symposium (ATS), 2005, pp. 242-247 https://doi.org/10.1109/ATS.2005.87
- Seongmoon Wang, 'A BIST for Low Power Dissipation and High Fault Coverage', IEEE Trans. on VLSI, vol. 15, no. 7, July 2007, pp. 777-789 https://doi.org/10.1109/TVLSI.2007.899234
- S. Wang and K Gupta, 'LT-RTPG: A New Test-Per-Scan BIST TPG for Low Switching Activity ', IEEE Trans. on CAD, vol. 25, no. 8, Aug. 2006, pp. 1565-1574 https://doi.org/10.1109/TCAD.2005.855927
- Ahmad AI-Yamani, Narendra Devta-Prasanna Erik Chmelar, Mikhail Grinchuk, and Arun Gunda, 'Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration', IEEE Trans. on CAD, vol. 26, no. 5, May 2007, pp.907-918 https://doi.org/10.1109/TCAD.2006.884582
- Jayashree Saxena, Kenneth M. Butler, and Lee Whetsel, 'An Analysis of Power Reduction Techniques in Scan Testing', Proc. of IEEE International Test Conference (ITC) , 2001, pp. 670-677 https://doi.org/10.1109/TEST.2001.966687
- Paul M. Rosinger and Bashir M. Al-Hashimi, 'Scan Architecture for Shift and Capture Cycle Power Reduction', Proc. of International Symposium on Defect and Fault Tolerance in VLSI System, 2002, pp. 129-137 https://doi.org/10.1109/DFTVS.2002.1173509
- Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, and Hideo Fujiwara, "Improving Test Effectiveness of Scan-Based BIST by Scan Chain Partitioning", IEEE Trans. on CAD , 2005 , pp. 916-927 https://doi.org/10.1109/TCAD.2005.847943
- Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, "A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores", Proc. of IEEE Asian Test Symposium (ATS), 2001, pp. 253-258 https://doi.org/10.1109/ATS.2001.990291
- Swarup Bhunia, Hamid Mahrnoodi , DebjyotiGhosh, and Kaushik Roy, 'Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning', Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), 2005, pp. 453-458 https://doi.org/10.1109/ISQED.2005.96
- S. Wang, and K Gupta, 'DS-LFSR : A New BIST TPG for Low Heat Dissipation', Proc. IEEE International Test Conference (ITC) , 1997, pp. 848-857 https://doi.org/10.1109/TEST.1997.639699
- Youbean Kim, Kicheol Kim, Incheol Kim, HyeonUk Son and Sungho Kang, 'A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-random Logic BIST', IEICE Information and Systems, vol. E01-D, no. 4, April 2008, pp. 1185-1188
- KM. Butler, ''Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Technique', Proc. of IEEE International Test Conference (ITC) , 2004, pp. 355-364 https://doi.org/10.1109/TEST.2004.1386971
- Nadir Z. Basturkmen, Sudhakar M. Reddy, and Irith Pomeranz, "A Low Power Pseudo-Random BIST Technique", Proc. IEEE International On-Line Testing Symposium (IOLTS), 2002, pp. 140-144 https://doi.org/10.1109/ICCD.2002.1106815
- S. Gupta, ]. Raj ski, and ]. Tyszer, 'Arithmetic additive generators of pseudo-exhaustive test patterns', IEEE Trans. on Computers, vol. 45, no. 8, Aug. 1996, pp.939-949 https://doi.org/10.1109/12.536236