대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

표준 CMOS 게이트 산화막 안티퓨즈를 이용한 새로운 OTP 단위 비트와 ROM 설계

Design of Novel OTP Unit Bit and ROM Using Standard CMOS Gate Oxide Antifuse

  • 신창희 (한양대학교 전자컴퓨터통신공학과) ;
  • 권오경 (한양대학교 전자컴퓨터통신공학과)
  • Shin, Chang-Hee (Department of Electronics Computer Engineering, Hanyang University) ;
  • Kwon, Oh-Kyong (Department of Electronics Computer Engineering, Hanyang University)
  • 발행 : 2009.05.25
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초록

표준 CMOS 공정을 이용한 CMOS 게이트 산화막 안티퓨즈의 새로운 OTP 단위 비트 구조를 제안하였다. 제안된 OTP 단위 비트는 NMOS 게이트 산화막 안티퓨즈를 포함한 3개의 트랜지스터와 인버터 타입 자체 센스 엠프를 포함하고 있다. 그럼에도 불구하고, 레이아웃 면적은 기존 구조와 비슷한 $22{\mu}m^2$이다. 또한, 제안된 OTT 단위 비트는 구조적 특징상 고전압 차단스위치 트랜지스터와 저항과 같은 고전압 차단 요소를 사용하지 않기 때문에, 프로그램 시간은 기존 구조보다 개선된 3.6msec이다. 그리고 제안된 OTP 단위 비트를 포함하는 OTP array는 센스 엠프가 단위 비트마다 집적되어 있기 때문에 기존 OTP array에서 사용된 센스 엠프와 바이어스 생성 회로가 필요 없다.

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

키워드

참고문헌

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