참고문헌
- T. Paul and T. Ogunfumni, "WIreless LAN Comes of Age: Understanding the IEEE 802.11n Amendment," in IEEE Circuits and Systems Magazine, pp. 28-54, Jan. 2008
- Y. Park, S. Kartl:llkeyan, F. Tsay, and E. Bartolome, "A 10b 100MSample/s CMOS Pipelined ADC with 1.8V Power Supply," in ISSCC Dig. Tech Papers, Feb. 2001, pp. 580-583
- M. Boulemnakher, E. Andre, J. Roux, and F. Paillardet, "A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS," in ISSCC Dig. Tech Papers, Feb. 2008, pp. 250-251
- S. Shin, Y. You, S. Lee, K Moon, and J. Kim, "A Fully-Differential Zero-Crossing-Based 1.2V 10b 26MS/s Pipelined ADC in 65nm CMOS," in Symp. VISI Circuits Dig. Tech Papers, Jun. 2008, pp. 218-219
- J. Hu, N. Dolev, and B. Munnann, "A 9.4-bit, 50-MS/s, L44-mW Pipelined ADC using Dynamic Residue Amplification," in Symp. VISI Circuits Dig. Tech Papers, Jun. 2008, pp. 216-217
- P. N. Singh, A Kumar, C. Debnath, and R. Malik, "A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process," in Proc CICC, Sept. 2008, pp. 305-308
- K. EI-Sankary and M. Sawall, "10-b 100-MS/s Two-Channel Time-Interleaved Pipelined ADC," in PrOG. CICC, Sept. 2006, pp. 217-220
- K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, "A 250-mW, 8-b, 52-Msamples/s para11el-pipelined AID converter with reduced number of amplifiers," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 312-320, Mar. 1997 https://doi.org/10.1109/4.557628
- J. Li, X. Zeng, L. Xie, J. Chen, J. Zhang, and Y. Guo, "A 1.8-V 22-mW 10-bit 30-MS/s Pipelined ADC for Low-Power Subsampling Applications," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 321-329, Mar. 2008 https://doi.org/10.1109/JSSC.2007.914253
- P. C. Yu, and H. Lee, "A 2.5-V, 12-b, 5-MSample/s Pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996 https://doi.org/10.1109/4.545805
- S. Ryu, B. Song, and K Bacrania, "A 10-bit 50-MS/s Pipelined ADC With Op amp Current Reuse," IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 475-485, Mar. 2007 https://doi.org/10.1109/JSSC.2006.891718
- B. Min, P. Kim, D. Boisvert, and A Aude, "A 69mW 10b 80-MS/s Pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031-2039, Dec. 2003 https://doi.org/10.1109/JSSC.2003.819166
- Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, Dec. 2004 https://doi.org/10.1109/JSSC.2004.836232
- M. Waltari and K. A. I. Halonen, "l-V 9-Bit Pipelined Switched-Op amp ADC," IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 129-134, Jan. 2001 https://doi.org/10.1109/4.896237
- H. Kim, D. Jeong, and W. Kim, "A 30mW 8b 200MS/s Pipelined CMOS ADC Using a Switched-Op amp Technique," in ISSCC Dig. Tech Papers, Feb. 2005, pp. 284-285
- W. Song, H. Choi, S. Kwak, and B. Song, "A 10-b 20-Msample/s low-power CMOS ADC," IEEE J. Solid-State Circuits, vol. 30, no. 5, pp. 514-521, May 1995 https://doi.org/10.1109/4.384164
- C. Lane, "A 10-bit 60 Msps flash ADC," in Proc. Bipolar Circuits and Technology Meeting, Sept. 1989, pp. 44-47
- H. Alzaher and M. Ismail, "A CMOS fully balanced differential difference amplifier and its application," IEEE Transactions on Circuit and Systems II, vol. 48, no. 6, pp. 614-620, Jun. 2001 https://doi.org/10.1109/82.943332
- P. Figueiredo and J. C. Vital, "Kickback noise reduction technique for CMOS latched comparators," IEEE Transactions on Circuit and Systems II, vol. 53, no. 7, pp. 541-545, Jul. 2006 https://doi.org/10.1109/TCSII.2006.875308
- M. Boulemnakher, E. Andre, J. Roux, and F. Paillardet, "A 1.2V 4.5mW 10b looMS/s Pipeline ADC in a 65nm CMOS," in ISSCC Dig. Tech Papers, Feb. 2008, pp. 250-251
- K. Honda, M. Furuta, and S. Kawahito, "A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline M) Converter Using Capacitance Coupling Techniques," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 757-765, April. 2007 https://doi.org/10.1109/JSSC.2007.891683
- Young-Ju Kim, et al., "A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC," in Pmc CICC, Sept. 2007, pp. 185-188