대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

저항 및 커패시턴스 스케일링 구조를 이용한 위상고정루프

A Phase Locked Loop with Resistance and Capacitance Scaling Scheme

  • 송윤귀 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 최영식 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 류지구 (부경대학교 전자컴퓨터정보통신공학부)
  • Song, Youn-Gui (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University) ;
  • Choi, Young-Shig (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University) ;
  • Ryu, Ji-Goo (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
  • 발행 : 2009.04.25
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초록

본 논문에서는 다중 전하펌프를 이용하여 저항과 커패시턴스 크기를 변화시키는 구조의 새로운 위상고정루프를 제안하였다. 제안된 위상고정루프는 세 개의 전하펌프를 사용하여 루프필터의 실효 커패시턴스와 저항을 위상고정 상태에 따라 각 전하펌프의 전류량 크기와 방향 제어를 통해 증감시킬 수 있다. 이러한 구조는 좁은 대역폭과 작은 루프 필터 저항 값을 가능하게 하여 좋은 잡음 특성과 기준 주파수 의사 잡음 특성을 가지도록 한다. 제안된 위상고정루프는 3.3V $0.35{\mu}m$ CMOS 공정을 이용하여 제작되었다. 851.2MHz 출력 주파수에서 측정된 위상 잡음은 -105.37 dBc/Hz @1MHz이며, 기준 주파수 의사 잡음은 -50dBc이다. 측정된 위상고정시간은 $25{\mu}s$이다.

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

키워드

참고문헌

  1. Marianne M. KAMAL, Emad W. EL -SHEWEKH, and Muhammad H. EL -SABA, "Design and implementation of a low-phase-noise integrated CMOS Frequency Synthesizer for highsensitivity narrow-band FM transceivers," Microelectronics, pp. 167-175, Cairo, Egypt. Dec. 2003
  2. Yan Ge, Wennan Feng, Zhongjian Chen, Song Jia and Lijiu Ji, "A Fast Locking Charge-Pump PLL with Adaptive Bandwidth," ASIC. vol. 1, ASICON, pp. 431-434, Oct. 2005
  3. Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim and Beomsup Kim, "A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 807-815, June. 2000 https://doi.org/10.1109/4.845184
  4. Tsung-Hsien Lin and William J. Kaiser, "A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 424-431, March. 2001 https://doi.org/10.1109/4.910481
  5. Shen Ye, Lars Jansson and Ian Galton, 'A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise,' IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, December. 2002 https://doi.org/10.1109/JSSC.2002.804339
  6. T.H. Lin and W. J. Kaiser, "A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop," IEEE J. Sloid-State Circuits, vol. 36, no. 3, pp. 424-431, Mar. 2001 https://doi.org/10.1109/4.910481
  7. C. Y. Yang and S. I. Liu, "Fast-switching frequency synthesizer with a discriminator-aided phase detector" IEEE J. Sloid-State Circuits, vol. 35, pp. 1445-1452, Oct. 2000 https://doi.org/10.1109/4.871321
  8. 권태하, 'Capacitance Scaling 구조와 여러 개의 전하펌프를 이용한 고속의 $\Sigma$$\Delta$ Fractional-N PLL', 대한전자공학회지, vol. 43, pp. 90-96, 2006
  9. Chan-Hong Park and Beomsup Kim, "A Low-Noise, 900-MHz VCO in 0.6-$\mu$m CMOS," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 586-591, May. 1999 https://doi.org/10.1109/4.760367