한국정보과학회논문지:시스템및이론 (Journal of KIISE:Computer Systems and Theory)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
권호 표지

On-Chip SRAM을 이용한 임베디드 시스템 메모리 계층 최적화

Memory Hierarchy Optimization in Embedded Systems using On-Chip SRAM

  • 김정원 (서울대학교 컴퓨터공학부) ;
  • 김승균 (서울대학교 컴퓨터공학부) ;
  • 이재진 (서울대학교 컴퓨터공학부) ;
  • 정창희 ;
  • 우덕균 (한국전자통신연구원 센서네트워크플렛폼연구팀)
  • 발행 : 2009.04.15
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⟨ 이전 논문 다음 논문 ⟩

초록

컴퓨터 시스템 분야의 대표적인 문제 중 하나는 메모리의 처리 속도가 CPU의 처리 속도보다 매우 느리기 때문에 생기는 CPU 휴면 시간의 증가, 즉 메모리 장벽 문제이다. CPU와 메모리의 속도 차이를 줄이기 위해서는 레지스터, 캐시 메모리, 메인 메모리, 디스크로 대표되는 메모리 계층을 이용하여 자주 쓰이는 데이터를 메모리 계층 상위, 즉 CPU 가까이 위치시켜야 한다. 본 논문에서는 On-Chip SRAM을 이용한 임베디드 시스템 메모리 계층 최적화 기법을 리눅스 기반 시스템에서 최초로 제안한다. 본 기법은 시스템의 가상 메모리를 이용하여 프로그래머가 원하는 코드나 데이터를 On-Chip SRAM에 적재한다. 제안된 기법의 실험 결과 총 9개의 어플리케이션에 대하여 최대 35%, 평균 14%의 시스템 성능 향상과 최대 40% 평균 15%의 에너지 소비 감소를 보였다.

The memory wall is the growing disparity of speed between CPU and memory outside the CPU chip. An economical solution is a memory hierarchy organized into several levels, such as processor registers, cache, main memory, disk storage. We introduce a novel memory hierarchy optimization technique in Linux based embedded systems using on-chip SRAM for the first time. The optimization technique allocates On-Chip SRAM to the code/data that selected by programmers by using virtual memory systems. Experiments performed with nine applications indicate that the runtime improvements can be achieved by up to 35%, with an average of 14%, and the energy consumption can be reduced by up to 40%, with an average of 15%.

키워드

참고문헌

  1. John Hennessy and David Patterson. Computer Architecture A Quantitative Approach. Morgan Kaufmann, Third deition, 2002.
  2. Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, and Peter Marwedel. Scratchpad Memory: A Design Alternative for Cache Onchip memory in Embedded Systems. In Proceedings of the 10th International Workshop on Hardware/Software Codesign, pages 73-78, May 2002.
  3. Oren Avissar, Rajeev Barua, and Dave Stewart. An Optimal Memory Allocation Scheme for Scratch-Pad Based Embedded Systems. ACM Transactions on Embedded Computing systems, pages 6-26, November 2002.
  4. Bernhard Eger, Chihun Kim, Choonki Jang, Yoonsung Nam, Jaejin Lee, and Sang Lyul Min. A dynamic code placement technique or scrathpad memory using postpass optimization. In Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, pages 223-233, October 2006.
  5. Bernhard Egger, Jaejin Lee, and Heonshik Shin. Scratchpad memory management for portable systems with a memory management unit. In Proceedings of the 6th ACM & IEEE International conference on Embedded software, pages 321-330, October 2006.
  6. Hyeongmin Cho, Bernhard Egger, Jaejin Lee, and Heonshik Shin. Dynamic Data Scratchpad Memory Management for a Memory Subsystem with and MMU. In Proceedings of the International Conference on Languages, Compilers, and Tools for Embedded Systems, pages 196-206, June 2007.
  7. Bernhard Egger, Jaejin Lee, and Heonshik Shin. Dynamic scratchpad memory management for code in portable systems with and MMU. ACM Transactions on Embedded Computing System, Volume 7, Issue 2, pages 1-38, 2008.
  8. Bernhard Eger, Jaejin Lee, and Heonshik Shin. Scratchpad memory management in a multitasking environment. In Proceedings of the 7th ACM international conference on Embedded software, pages 265-274, October 2008.
  9. Nghi Nguyen, Angel Dominguez, and Rajeev Barua. Scratch-pad memory allocation without compiler support for fava applications. In Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 85-94, October 2007.
  10. Marvell, Marvellⓡ PXA30x Processor and PXA31xProcessor, Volume II: Memory Controller Configuration Developers Maunal, Doc. No. MV-S301038-02, Rev. B. 2007.
  11. TIS Committee, Tool Interface Standard (TIS) Executable and Linking Format (ELF) Specification Version 1.2, 1995.
  12. Intel, Intelⓡ PXA27x Processor Family Optimization Guide, 2004.
  13. Mark Allen Weis. Data Stuctures and Algorithem Analysis in C, Addison-Wesley, 1997.
  14. EEMBC-The Embedded Microprocessor Benchmark Consortium, http://eembc.org.
  15. gzip, http://www.gzip.org.
  16. Agilent Technologies, Agilent E3634A, http://www.home.agilent.com/agilent/product.jspx?nid-35690.384003.00.
  17. National Instruments, NI PCI-6259, http://sine.ni.som/nips/cds/view/p/lang/en/nid/14128