참고문헌
- Knickerbocker, J. U., Andry, P. S., Dang, B., Horton, R. R., Patel, C. S., Polastre, R. J., Sakuma, K., Sprogis, E. S., Tsang, C. K., Webb, B. C. and Wright, S. L., "3D Silicon Integration," 58th Electronic Components and Technology Conference, pp. 538-543, 2008
- Thompson, S. E., Sun, G., Choi, Y. S. and Nishida, T., "Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap," IEEE Trans. Electron Devices, Vol. 53, No.5, pp. 1010-1020, 2006 https://doi.org/10.1109/TED.2006.872088
- Wunderle, B., Mrossko, R., Wittler, O., Kaulfersch, E., Ramm, P., Michel, B. and Reichl, H., "Thermo-Mechanical Reliability of 3D-Integrated Microstructures in Stacked Silicon," Mater. Res. Soc. Symp. Proc., Vol. 970, 2007
- Zhang, J., Bloomfield, M. O., Lu, J.-Q., Gutmann, R. J. and Cale, T. S., "Modeling Thermal Stresses in 3-D IC Interwafer interconnects," IEEE Trans. on Semicondutor Manufacturing, Vol. 19, No.4, pp. 437-448, 2006
- Lu, K., Zhang, Z., Ryu, S., Huang I. R. and Ho, P. S., "Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias," Electronic Components and Technology Conference, pp. 630-634, 2009
- Hsieh, M. C. and Yu, C. K., "Thermo-mechanical Simulations For 4-Layer Stacked IC Packages," International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems, 2008
- Selvanayagam, C. S., Lau, J. H., Zhang, X., Seah, S. K. W., Vaidyanathan, K. and Chai, T. C., "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV(Through Silicon Via) and their Flip-Chip Microbumps," Electronic Components and Technology Conference, pp. 1073-1081, 2008
- Ramm, P., Wolf, M. J., Klumpp, A., Wieland, R., Wunderle, B., Michel, B. and Reichl, H., "Through Silicon Via Technology-Processes and Reliability for Wafer-Level 3D System Integration," Electronic Components and Technology Conference, pp. 841-846, 2008
- Kitada, H., Maeda, N., Fujimoto, K., Suzuki, K., Kawai, A., Arai, K. and Suzuki, T., "Stress Sensitivity Analysis on TSV Structure of Wafer-on-a-Wafer(WOW) by Finite Element Method(FEM)," IEEE Interconnect Technology Conference, pp. 107-109, 2009
- Hsieh, M. C., Yu, C. K. and Lee, W., "Effects of Geometry and Material Properties for Stacked IC Package with Spacer Structure," 10th International Conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems, 2009
- Kannarkar, A. P., "Performance and Reliability Analysis of 3D-Integration Structures Employing Through Silicon Via (TSV)," International Reliability Physics Symposium, pp. 682-687, 2009
- Khan, N., "Development of 3D Silicon Module with TSV for System in Packaging," Electronic Components and Technology Conference, pp. 550-555, 2008
- Agarwal, R., Zhang, W., Limaye, P. and Ruythooren, W., "High Density Cu-Sn TLP Bonding for 3D integration," Electronic Components and Technology Conference, pp. 345-349, 2009
- Kim, E. S., Lee, J. M. and Kim. B. M., "Selection of the Optimum Seaming Condition for Spin Drum Using Statistical Method," Journal of the Korean Society for Precision Engineering, Vol. 25, No.1, pp. 99-107, 2008