Journal of Electrical Engineering and Technology

The Korean Institute of Electrical Engineers (대한전기학회)
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A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing

  • Kim, Jung-Tae (Leading Product PE/TEST Group, System LSI Division, Samsung Electronics, Korea and School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, In-Soo (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Keon-Ho (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Yong-Hyun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Baek, Chul-Ki (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kyu-Taek (Leading Product PE/TEST Group, System LSI Division, Samsung Electronics) ;
  • Min, Hyoung-Bok (School of Information and Communication Engineering, Sungkyunkwan University)
  • Published : 2009.12.01
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Abstract

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

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References

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