차동 연결된 Varactor를 이용한 6Gbps CMOS 피드포워드 이퀄라이저

A 6Gbps CMOS Feed-Forward Equalizer Using A Differentially-Connected Varactor

  • 발행 : 2009.02.25

초록

0.13-um CMOS 공정을 이용하여 3GHz에서 6.2dB의 gain을 갖는 피드포워드 이퀄라이저를 구현하고 14.7dB의 감쇄를 갖는 7-m SATA 케이블을 통해 6Gbps의 데이터를 에러 없이 복원하였다. 제안한 이퀄라이저 회로는 varactor의 차동 연결을 통해서 기존 이퀄라이저에서 사용되는 varactor 면적의 1/4만을 사용하도록 설계되어 pad-frame에 집적할 수 있을 뿐만 아니라, 높은 동작 주파수 및 3.6mW의 낮은 전력 소모를 유지할 수 있다.

A 6-Gbps feed-forward equalizer having a 6.2-dB gain at 3GHz is designed in 0.13-um CMOS technology and the equalizer helps error-free data recovery over a 7-m SATA cable with 14.7dB loss. Based on a differentially-connected varactor, the proposed equalizer uses only a one-fourth varactor size of a conventional equalizer, which enables the equalizer's integration in a pad-frame, high operating frequency, and low power dissipation of 3.6mW.

키워드

참고문헌

  1. PCI Express Base Specification Rev. 2.0, Feb. 2007
  2. Serial ATA Workgroup, 'Serial ATA II: Electrical Specification,' Rev. 2.6, Feb. 2007
  3. A J Baker, 'An Adaptive Cable Equalizer for Serial Digital Video Rates to 4OOMb/s,' in IEEE ISSCC Dig. Tech. Papers, pp. 174-175, Feb 1996
  4. J N. Babanezhad, 'A 3.3V Analog Adaptive Line-Equalizer for Fast Ethernet Data Communication,' Proc. IEEE Custom Integrated Ciratits Corif'., pp. 343-346, May 1998 https://doi.org/10.1109/CICC.1998.694995
  5. J-S. Choi, M-S. Hwang, and D.-K. Jeong, 'A O.l8um CMOS 3.5-Gb/s Continuous-time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Method,' IEEE J Solid-State Circuits, vol. 39, pp. 419-425, March 2004 https://doi.org/10.1109/JSSC.2003.822774
  6. G. Zhang, P. Chaudhari, and M M. Green, 'A BiCMOS lOGb/s Adaptive Cable Equalizer,' IEEE ISSCC Dig. Tech Papers, pp. 482-483, Feb 2004 https://doi.org/10.1109/ISSCC.2004.1332804
  7. Y. Tomita, M Kibune, J Ogawa, W. W. Walker, H. Tamura, and T. Kuroda, 'A lOGb/s Receiver with Equalizer and On-chip lSI Monitor in O.11um CMOS,' Symp. VLSI Circuits Dig. Tech Papers, pp. 202-205, June 2004
  8. M Soma, T. Beukema, K. Selander, S. Zier, B. Ji, P. Murfet, J Mason, W. Rhee, H. Ainspan, and B. Parker, 'A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization,' IEEE ISSCC Dig. Tech Papers, pp. 62-63, Feb 2005 https://doi.org/10.1109/ISSCC.2005.1493869
  9. S. Gondi, J Lee, D. Takeuchi, and B. Razavi, 'A lOGb/s CMOS Adaptive Equalizer for Backplane Applications,' IEEE ISSCC Dig. Tech Papers, pp. 328-329, Feb 2005 https://doi.org/10.1109/ISSCC.2005.1494002
  10. 이기혁, 성창경, 최우영,'위상 검출기 출력을 이용한 백플레인용 5Gbps CMOS 적응형 피드포워드이퀼라이저,' 전자공학회지논문지, 제44권 SD편, 제5호, 50-57쪽, 2007년 5월
  11. 유귀성, 한건희, 박성민, "백플레인용 lOGbps 아날로그 어댑티브 이퀄라이저," 전자공학회논문지, 제44권 SD편, 제9호, 34-39쪽, 2007년9월
  12. A-S. Porret, T. Melly, C. C. Enz, and E. A Vittoz, 'Design of High-Q Varactors for Low-Power WIreless Applications Using a Standard CMOS Process,' IEEE J Solid-State Circuits, vol. 35, pp. 337-345, March 2000 https://doi.org/10.1109/4.826815
  13. Y. Moon, G. Ahn, H. Choi, N. Kim, and D. Shim, 'A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control,' IEEE ISSCC Dig. Tech Papers, pp. 84-85, Feb 2006 https://doi.org/10.1109/ISSCC.2006.1696053