Journal of the Institute of Convergence Signal Processing (융합신호처리학회논문지)

The Korea Institute of Convergence Signal Processing (한국융합신호처리학회)
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Algorithm and Design of Double-base Log Encoder for Flash A/D Converters

  • Son, Nguyen-Minh (Electrical Engineering at the University of Ulsan) ;
  • Kim, In-Soo (Electrical Engineering at the Pennsylvania State University) ;
  • Choi, Jae-Ha (School of Electrical Engineering, University of Ulsan) ;
  • Kim, Jong-Soo (School of Electrical Engineering, University of Ulsan)
  • Published : 2009.10.30
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Abstract

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

Keywords

References

  1. Vassil S. Dimitrov and Graham A. Jullien, "A New Number Representation with applications", IEEE Circuits and Systems Magazine, 2003.
  2. Vassil S. Dimitrov and Graham A. Jullien, and W. C. Miller, "Theory and applications of the double-base number system", IEEE Transactions on Computers, vol. 48, pp. 1098 - 1106, 1999.
  3. G. Gilbert and J. M. P. Langlois, "Multipath greedy algorithm for canonical representation of numbers in the double base number system", IEEE-NEWCAS Conference, pp. 39-42, 19 - 22, June 2005.
  4. V. Berthe, Laurent Imbert, and Graham A. Jullien, "More on Converting Numbers to the Double-Base Number System", Research Report LIRMM - 0403 1, Montpellier France, October 2004.
  5. Y. Ibrahim, W. C. Miller, Graham A. Jullien, and Vassil S. Dimitrov, "DBNS addition using cellular neural networks", IEEE International Symposium on Circuits and Systems, vol. 4, pp. 3914 - 3917, 23 - 26 May 2005.
  6. M. Pankaala, A. Paasio, and M. Laiho, "Implementation alternatives of a DBNS adder", 9th International Workshop on Cellular Neural Networks and Their Applications, pp. 138 - 141, 28-30 May 2005.
  7. Kriangyut Wangjitman and Athasit Surarerks, "Addition transducer for double base number system", ISCIT'06, pp. 994-999, Sep 2006.
  8. Jincheol Yoo, "A TIQ Based CMOS Flash A/D Converter for SoC Applications", PhD Thesis Department of Computer Science and Engineering of The Pennsylvania State University, 2003.
  9. Daegyu Lee, Jincheol Yoo, Kyusun Choi and Jahan Ghaznavi, "Fat Tree Encoder design for Ultra-high speed Flash A/D Converters", The 45th Midwest Symposium on Circuits and Systems, vol. 2, pp. 87-90, Aug 2002.
  10. Jincheol Yoo, Daegyu Lee, Kyusun Choi and Jongsoo Kim, "A Power and Resolution Adaptive Flash Analog-to-Digital Converter", ISLPED'02, pp. 233-236, August 2002.
  11. Daegyu Lee, Jincheol Yoo, Kyusun Choi, "Design Method and Automation of Comparator Generation for Flash A/D Converter", IEEE International Symposium on Quality Electronic Design, pp 138-142, March 2002.
  12. D.P. Dimitrov and T. K. Vasileva, "8-bit semi Flash A/D Converter", Proceedings of the International Conference Mixed Design of Integrated Circuits and System, pp. 171-174, June 2006.
  13. Jongsoo Kim, Man-Ho Kim, Eun-Hwa Jang, "A New Flash A/D Converter Adopting Double Base Number System", KISPS Journal of Signal Processing and Systems, vol. 9, no. 1, pp. 54-61, 2008.
  14. Minh Son Nguyen, Soo A Yeo, Man-Ho Kim and Jongsoo Kim, "Application of Constraint Algorithm for High Speed A/D Converters", KISPS Journal of Signal Processing and Systems, vol. 9, no. 3, pp. 224-229, 2008.
  15. Minh Son Nguyen, Man-Ho Kim and Jongsoo Kim, "Constraint Algorithm in Double-base Number System for High Speed A/D Converters", Journal of Electrical Engineering and Technology, vol. 3, no. 3, pp. 430-435, 2008. https://doi.org/10.5370/JEET.2008.3.3.430
  16. Minh Son Nguyen, Insoo Kim, Kyusun Choi and, Jongsoo Kim, "Design and Implementation of Double-base Integer Encoder in the Flash ADC", 2009 6th International Conference on Electrical Engineering /Electronics, Computer, Telecommunications and Information Technology, vol. 1, pp. 496-499, 2009.
  17. Neil H.E. Weste and David Harris, "CMOS VLSI design-A circuits and systems perspective", 3rd edition, Addison-Wesley, 2004.
  18. R Jacob Baker, "CMOS: Circuit Design, Layout, and Simulation", 2nd edition, Wiley-IEEE, 2005.