Transactions on Electrical and Electronic Materials

  • 제10권6호
  • /
  • Pages.193-195
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  • 2009
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  • 1229-7607(pISSN)
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  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Development of Low-Vgs N-LDMOS Structure with Double Gate Oxide for Improving Rsp

  • Jeong, Woo-Yang (Department of Semiconductor System, Korea Polytechnic College IV) ;
  • Yi, Keun-Man (Department of Electrical and Electronics Engineering, Cheong-ju University)
  • 발행 : 2009.12.31
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초록

This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

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참고문헌

  1. C. Y. Lu, M. C. Morgan, and N. S. Tsai, Solid State Electron. 30, 793 (1987) https://doi.org/10.1016/0038-1101(87)90003-7
  2. C.-J. Ko, S.-Y. Lee, I.-Y. Park, C.-E. Park, B.-K. Jun, Y.-J. Lee, C.-H. Kang, J.-O. Lee, N.-J. Kim, and K.-D. Yoo, Proceedings of International Symposium Power Semiconductor Device & ICs, (IEEE, San Francisco CA, 2005), p. 103
  3. G. Haberfehlner, S. Bychikhin, V. Dubec, M. Heer, A. Podgaynaya, M. Pfost, M. Stecher, E. Gornik, and D. Pogany, Microelectronics Reliability, 49, 1346 (2009) https://doi.org/10.1016/j.microrel.2009.07.032
  4. B. Wang, H. Nguyen, J. Mavoori, A. Horch, Y. Ma, T. Humes, and R. Paulse, Proceedings of International Reliability Physics Symposium, (IEEE, San Jose Marriott in San Jose, 2005), p. 654
  5. K.-Y.l Na and Y.-S. Kim, Curr. Appl. Phys. 9, 9 (2009) https://doi.org/10.1016/j.cap.2007.10.086
  6. T. M. Roh, D. W. Lee, Q. S. Song, J. Kim, J.-Y. Kang, J. G. Koo, and K. S. Nam, J. Korean Phys. Soc. 33, S235 (1998)
  7. W. Fulop, Solid State Electron.10, 39 (1997) https://doi.org/10.1016/0038-1101(67)90111-6