참고문헌
- H.-S. P. Wong, "Beyond the conventional transistor," IBM J. Res. & Dev., Vol.46, No.2/3, pp.133-167, May 2002 https://doi.org/10.1147/rd.462.0133
- D. A. Buchanan, "Beyond microelectronics: materials and technology for nano-scale CMOS devices," phys. stat. sol. (c) 1, No. S2, pp.S155-S162, 2004 https://doi.org/10.1002/pssc.200405135
- International Technology Roadmap in Semiconductors (ITRS)
- F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Lett., Vol.ED-8, pp.410-412, Sept. 1987
- J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, "Silicon-on-insulator gateall- around device," in IEDM Tech. Dig., pp.595- 598, 1990
- D. Hisamoto, T. Kaga, and E. Takeda, "Impact of the vertical SOI 'Delta' structure on planar device technology," IEEE Trans. Electron Devices, Vol.38, pp.1419-1424, June 1991 https://doi.org/10.1109/16.81634
- B. Majkusiak, T. Janik, and J. Walczak, "Semiconductor thickness effects in the double-gate SOI MOSFET," IEEE Trans. Electron Devices, Vol.45, No.5, pp.1127-1134, May 1998 https://doi.org/10.1109/16.669563
- H.-S. Wong, D. Frank, and P. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation," in IEDM Tech. Dig., pp.407-410, 1998
- F. Gamiz and M. V. Fischetti, "Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion," J. Appl. Phys., Vol.89, pp.5478-5487, 2001 https://doi.org/10.1063/1.1358321
-
F. Gamiz, J. B. Roldan, A. Godoy, and F. Jimenez- Molinos, "Double gate silicon-on-insulator transistors:
$n^+-n^+$ gate versus n+-p+ gate configuration," in Proc. IEEE ESSDERC, pp.173-176, 2004 -
K. Uchida , J. Koga, and S. Takagi, "Experimental study on carrier transport mechanisms in doubleand single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and
$\delta$ TSOI-induced scattering," in IEDM Tech. Dig., pp.805-808, 2003 - D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "An Experimental Study of Mobility Enhancement in Ultrathin SOI Transistors Operated in Double-Gate Mode," IEEE Trans. Electron. Devices, Vol.50, No.3, pp.802-808, Mar. 2003 https://doi.org/10.1109/TED.2002.807444
- G. Tsutsui , M. Saitoh, T. Saraya, T. Nagumo, and T. Hiramoto, "Mobility enhancement due to volume inversion in (110)-oriented ultra-thin body doublegate nMOSFETs with body thickness less than 5 nm," in IEDM Tech. Dig., pp.747-750, 2005
- V. Sverdlov, E. Ungersboeck, H. Kosina, and S. Selberherr, "Volume inversion mobility in SOI MOSFETs for different thin body orientations," Solid-State Electron., Vol.51, pp.299-305, 2007 https://doi.org/10.1016/j.sse.2007.01.022
- S. Takagi, J. Koga, and A. Toriumi, "Subband structure engineering for performance enhancement of Si MOSFETs," in IEDM Tech. Dig., pp.219-222, 1997
- F. Gamiz, J. A. Lopez-Villanueva, J. B. Roldan, J. E. Carceller, and P. Cartujo, "Monte Carlo Simulation of Electron Transport Properties in Extremely Thin SOI MOSFET's," IEEE Trans. Electron. Devices, Vol.45, pp.1122-1126, May 1998 https://doi.org/10.1109/16.669557
- M. Shoji and S. Horiguchi, "Electronic structures and phonon-limited electron mobility of doublegate silicon-on-insulator Si inversion layers," J. Appl. Phys., Vol.85, No.5, pp.2722-2731, 1999 https://doi.org/10.1063/1.369589
- D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application," IEEE Trans. Electron. Devices, Vol.48, No.12, pp.2842-2850, Dec. 2001 https://doi.org/10.1109/16.974714
- K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, "Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm," in IEDM Tech. Dig., pp.47-50, 2002
-
R. People, "Physics and applications of
$Ge_xSi_{1-x}/Si $ strained-layer heterostructures," J. Quant. Elec., Vol.QE-22, pp.1696-1710, 1986 - M. V. Fischetti and S. E. Laux, "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys," J. Appl. Phys., Vol.80, No.4, pp.2234-2252, 1996 https://doi.org/10.1063/1.363052
- P. R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise, "Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing," IEEE Trans. Electron Devices, Vol.53, No.5, pp.944-964, May 2006 https://doi.org/10.1109/TED.2006.872912
- D. Rideau, M. Feraille, L. Ciampolini, M. Minondo, C. Tavernier, H. Jaouen, and A. Ghetti, "Strained Si, Ge, and Si1-xGex alloys modeled with a firstprinciples- optimized full-zone k.p method," Phys. Rev. B, Vol.74, No.19, pp.195208-1-195208-20, 2006 https://doi.org/10.1103/PhysRevB.74.195208
- M. V. Fischetti, F. Gamiz, and W. Hänsch, "On the enhanced electron mobility in strained-silicon inversion layers," J. Appl. Phys., Vol.92, No.12, pp.7320-7324, 2002 https://doi.org/10.1063/1.1521796
- M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, "Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., Vol.97, No.011101, pp.1-27, 2005 https://doi.org/10.1007/10828028_1
- T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, et al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," in IEDM Tech. Dig., pp.978-980, 2003
- K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, et al., "Delaying forever: Uniaxial strained silicon transistors in a 90 nm CMOS technology," in VLSI Symp. Tech. Dig., pp. 50-51, 2004
- S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, "Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap," IEEE Trans. Electron Devices, Vol.53, No.5, pp.1010-1020, May 2006 https://doi.org/10.1109/TED.2006.872088
- S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, et al., "Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs," in IEDM Tech. Dig., pp.57-60, 2003
- T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, S. Takagi, "High performance strained-SOI CMOS devices using thin film SiGe-on-insulator technology," IEEE Trans Electron Devices, Vol.50, No.4, pp. 988-994, 2003 https://doi.org/10.1109/TED.2003.812149
- T. A. Langdo, M. T. Currie, A. Lochtefeld, R. Hammond, J. A. Carlin, M. Erdtmann, et al., "SiGefree strained Si on insulator by wafer bonding and layer transfer," Appl. Phys. Lett., Vol.82, No.24, pp.4256-4258, June 2003 https://doi.org/10.1063/1.1581371
- K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, et al., "Fabrication and mobility charac teristics of ultra-thin strained-Si directly on insulator (SSDOI) MOSFETs," in IEDM Tech. Dig., pp.49- 52, 2003
- I. Aberg, O.O. Olubuyide, C.N. Chleirigh, I. Lauer, D.A. Antoniadis, J. Li, R. Hull, and J.L. Hoyt, "Electron and hole mobility enhancements in sub- 10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-back technique," in VLSI Symp. Tech. Dig., pp.52-53, 2004
- W. F. Clark, D. M. Fried, L. D. Lanzerotti, and E. J. Nowak, "Strained FIN FETS structure and method," U.S. Patent 6 635 909 B2, October 21, 2003
- N. Barin, C. Fiegna, E. Sangiorgi, "Analysis of strainedsilicon- on-insulator double-gate MOS structures," in Proc. IEEE ESSDERC, pp.169-172, 2004
- T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, and S. Takagi., "(110)-Surface strained- SOI CMOS devices," IEEE Trans. Electron Devices, Vol.52, No.3, pp.367-374, Mar. 2005 https://doi.org/10.1109/TED.2005.843894
- T. Krishnamohan, D. Kim, C. D. Nguyen, C. Jungemann, Y. Nishi, and K. C. Saraswat, "Highmobility low band-to-band-tunneling strained-germanium double-gate heterostructure FETs: simulations," IEEE Trans. Electron Devices, Vol.53, No.5, pp. 1000-1009, May 2006
- P. Palestri, N. Barin, D. Brunel, C. Busseret, A. Campera, P. A. Childs, et al., "Comparison of Modeling Approaches for the Capacitance-Voltage and Current-Voltage Characteristics of Advanced Gate Stacks," IEEE Trans. Electron Devices, Vol.54, No.1, pp.106-114, Jan. 2007 https://doi.org/10.1109/TED.2006.887226
- L. Yang, J. R. Watling, R. C. W Wilkins, M. Boriçi, J. R. Barker, A. Asenov, and S. Roy, "Si/SiGe heterostructure parameters for device simulations," Semicond. Sci. Technol., Vol.19, pp.1174-1182, 2004 https://doi.org/10.1088/0268-1242/19/10/002
-
V. Venkataraman, C. W. Liu, and J. C. Sturm, "Alloy scattering limited transport of two-dimensional carriers in strained
$Si_{1-x}Ge_x$ quantum wells," Appl. Phys. Lett., Vol.63, No.20, pp.2795-2797, 1993 https://doi.org/10.1063/1.110337 - D. Vasileska and S. S. Ahmed, "Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation," IEEE Trans. Electron Devices, Vol.52, pp.227-236, February 2005 https://doi.org/10.1109/TED.2004.842715
- M. V. Fischetti, "Long-range Coulomb interactions in small Si devices. Part II. Effective electron mobility in thin-oxide structures," J. Appl. Phys., Vol.89, No.2, pp.1232-1250, 2001 https://doi.org/10.1063/1.1332424
- W.J. Gross, D. Vasileska, and D.K. Ferry, "Ultrasmall MOSFETs: the importance of the full Coulomb interaction on device characteristics," IEEE Trans. Electron. Devices, Vol.47, No.10, pp.1831-1837, Oct. 2000 https://doi.org/10.1109/16.870556
- S-I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, "Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor fieldeffect transistors," J. Appl. Phys., Vol.80, No.3, pp.1567-1577, 1996. https://doi.org/10.1063/1.362953
- C. Jacoboni and L. Reggiani, "The Monte Carlo method for the solution of charge transport in semiconductors with applications to covalent materials," Rev. Mod. Phys., Vol.55, No.3, pp.645-705, 1983 https://doi.org/10.1103/RevModPhys.55.645
- T. Ando, A. B. Fowler, and F. Stern., "Electronic properties of two-dimensional systems," Rev, Mod. Phys., Vol.54, pp.437-672, 1982 https://doi.org/10.1103/RevModPhys.54.437
-
F. Gamiz, J. B. Roldan, J. A. Lopez-Villanueva, P. Cartujo-Cassinello, and J. E. Carceller, "Surface roughness at the
$Si-SiO_2$ interfaces in fully depleted silicon-on-insulator inversion layers," J. Appl. Phys., Vol.86, No.12, pp.6854-6863, 1999 https://doi.org/10.1063/1.371763 - M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, "Six-band k.p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness," J. Appl. Phys., Vol.94, No.2, pp.1079-1095, 2003 https://doi.org/10.1063/1.1585120
-
S. M. Goodnick, D. K. Ferry, C. W. Wilmsen, Z. Liliental, D. Fathy, and O. L. Krivanek, "Surface roughness at the Si(100)-
$SiO_2$ interface," Phys. Rev. B, Vol.32, No.12, pp.8171-8186, 1985 https://doi.org/10.1103/PhysRevB.32.8171 - J. Li and T.-P. Ma, "Scattering of silicon inversion layer electrons by metal/oxide interface roughness," J. Appl. Phys., Vol.62, No.10, pp.4212-4215, 1987 https://doi.org/10.1063/1.339092
-
J. Walczak and B. Majkusiak, "The remote roughness mobility resulting from the ultrathin
$SiO_2$ thickness nonuniformity in the DG SOI and bulk MOS transistors," Microelectronic Engineering, Vol.59, No.1-4, pp.417-421, 2001 https://doi.org/10.1016/S0167-9317(01)00633-5 - F. Gamiz, A. Godoy, F. Jimenez-Molinos, P. Cartujo-Cassinello, and J. B Roldan, "Remote sur face roughness scattering in ultrathin-oxide MOSFETs," in Proc. IEEE ESSDERC, pp.403-406, 2003
- A. Gold, "Electronic transport properties of a twodimensional electron gas in a silicon quantum-well structure at low temperature," Phys. Rev. B, Vol.35, No.2, pp.723-733, 1987 https://doi.org/10.1103/PhysRevB.35.723
- H. Sakaki, T. Noda, K. Hirakawa, M. Tanaka, and T. Matsusue, "Interface roughness scattering in GaAs/ AlAs quantum wells," Appl. Phys. Lett., Vol. 51, No.23, pp.1934-1936, 1987 https://doi.org/10.1063/1.98305
- C-Y. Mou and T-m. Hong, "Transport in quantum wells in the presence of interface roughness," Phys. Rev. B, Vol.61, No.19, pp.12612-12615, 2000 https://doi.org/10.1103/PhysRevB.61.12612
- K. Uchida and S. Takagi, "Carrier scattering induced by thickness fluctuation of silicon-oninsulator film in ultrathin-body metal-oxide-semiconductor field-effect transistors," Appl Phys Let., Vol.82, No.17, pp.2916-2918, 2003 https://doi.org/10.1063/1.1571227
- D. Esseni, A. Abramo, L. Selmi, and E. Sangiorgi, "Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n- MOSFETs," IEEE Trans. Electron. Devices, Vol. 50, No.12, pp.2445-2455, Dec. 2003 https://doi.org/10.1109/TED.2003.819256
- T. Low, Li Ming-Fu, G. Samudra, Yeo Yee-Chia, Zhu Chunxiang, A. Chin, and Kwong Dim-Lee, "Modeling study of the impact of surface roughness on silicon and germanium UTB MOSFETs," IEEE Trans. Electron. Devices, Vol.52, No.11, pp.2430-2439, Nov. 2005 https://doi.org/10.1109/TED.2005.857188
- F. Monsef, P. Dollfus, S. Galdin-Retailleau, H.-J. Herzog, and T. Hackbarth, "Electron transport in Si'SiGe modulation-doped heterostructures using Monte Carlo simulation," J. Appl. Phys., Vol.95, No.7, pp.3587-3593, 2004 https://doi.org/10.1063/1.1650885
- L. Donetti, F. Gamiz, N. Rodriguez, F. Jimenez, and C. Sampedro, "Influence of acoustic phonon confinement on electron mobility in ultrathin silicon on insulator layers," Appl. Phys. Lett., Vol.88, No.12, pp.122108(1-3), 2006 https://doi.org/10.1063/1.2187952
피인용 문헌
- Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman's Method vol.52, pp.4, 2015, https://doi.org/10.5573/ieie.2015.52.4.056