저비용 내장형 멀티미디어 프로세서를 위한 분할 레지스터 접근 구조

A Partial Access Mechanism on a Register for Low-cost Embedded Multimedia ASIP

  • 조민영 (연세대학교 전기전자공학과) ;
  • 정하영 (연세대학교 전기전자공학과) ;
  • 이용석 (연세대학교 전기전자공학과)
  • Joe, Min-Young (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Jeong, Ha-Young (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Lee, Yong-Surk (Department of Electrical and Electronic Engineering, Yonsei University)
  • 발행 : 2008.09.25

초록

본 논문은 저비용 내장형 멀티미디어 프로세서를 위한 레지스터 분할 접근 구조를 제안한다. 저비용 내장형 시스템에서 SIMD 명령어 지원은 SIMD 지원 레지스터 파일과 실행유닛들의 추가에 따른 비용의 증가 때문에 적용이 어렵다. 제안한 구조는 하드웨어의 부담을 최소화하면서 SIMD 연산 수행을 지원하여 전체적인 성능을 향상 시킬 수 있는 구조다. ASIP을 설계하여 제안한 구조를 적용시켰으며 DSP 벤치마크에서 명령어 적용에 따른 실행 사이클의 변화를 비교하였다. 설계한 ASIP을 TSMC 0.25$\mu$m 공정으로 합성하여 제안한 구조 적용에 따른 면적 증가 및 전체적인 성능 향상을 분석하였다. 실험 결과 제안한 구조는 성능은 약 38% 향상되었고, 면적은 13.4% 증가하였다.

In this paper, we propose a partial access mechanism for low cost multimedia processors. Due to the cost increase of adding the SIMD register files and the execution blocks, we experience difficulties applying the SIMD instructions to low cost multimedia embedded processors. The proposed mechanism has the advantages of decreasing the cost burden of the additional hardware and enhancing total performance of the SIMD operation. We designed the ASIP in which the mechanism is applied and compared the latency of the SIMD operation regarding the use of instruction sets in the DSP benchmark. Then, we analyzed the total performance enhancement and the reduction in area burden by synthesizing the ASIP using 0.25um TSMC CMOS technology. As a result, there are approximately a 38% of performance increase and a 13.4% of area increase according to the proposed mechanism simulation.

키워드

참고문헌

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