대한전자공학회논문지SP (Journal of the Institute of Electronics Engineers of Korea SP)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

이진트리 비 균일 필터뱅크를 이용한 잡음감소기법 및 구현

A Noise De-Noising Technique using Binary-Tree Non-Uniform Filter Banks and Its Realization

  • Sohn, Sang-Wook (The Department of Electrical Engineering, Chungbuk National University) ;
  • Choi, Hun (Korea Research Institute of Standards and Science) ;
  • Bae, Hyeon-Deok (The Department of Electrical Engineering, Chungbuk National University)
  • 발행 : 2007.09.25
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초록

잠음감소에 있어서 웨이브렛 임계처리 알고리즘은 미니맥스 관점에서 거의 최적의 성능을 보이는 것으로 알려져 있다. 그러나 웨이브렛 임계처리 알고리즘은 웨이브렛 함수의 복잡성으로 인해 FPGA와 같은 하드웨어 상에 구현이 어렵다. 본 논문에서는 이진트리 구조 필터뱅크에서 전체 신호전력에 대한 각 부밴드 신호 전력비에 기반한 새로운 잡음감소 기법을 제안한다. 그리고 이 기법을 FPGA 상에 구현한다. 간단한 구현을 위해 필터뱅크는 하다마드 변환 계수로 설계된다. 시뮬레이션과 하드웨어 실험결과 제안방법이 간단하지만 웨이브렛에 기반한 소프트 임계처리 잡음감소 알고리즘과 성능이 유사함을 보인다.

In de-noising, it is wellknown that wavelet-thresholding algorithm shows near-optimal performances in the minimax sense. However, the wavelet-thresholding algorithm is difficult in realization it on hardware, such as FPGA, because of wavelet function complexity. In this paper, we present a new do-noising technique with the binary tree structured filter bank, which is based on the signal power ratio of each subbands to the total signal power. And we realize it on FPGA. For simple realization, the filter banks are designed by Hadamard transform coefficients. The simulation and hardware experimental results show that the performance of the proposed method is similar with that of soft thresholding de-noising algorithm based on wavelets, nevertheless it is simple.

키워드

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