한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제32권3C호
  • /
  • Pages.297-305
  • /
  • 2007
  • /
  • 1226-4717(pISSN)
  • /
  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
권호 표지

디지털 시네마용 Motion JPEG2000 인코더의 FPGA 설계

FPGA Design of Motion JPEG2000 Encoder for Digital Cinema

  • 서영호 (한성대학교 정보통신공학과) ;
  • 최현준 (광운대학교 전자재료공학과) ;
  • 김동욱 (광운대학교 전자재료공학과)
  • 발행 : 2007.03.31
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 주요 영화사들로 구성된 DCI(Digital Cinema Initiatives)에 의해 디지털 시네마를 위한 영상 압축 표준으로 제정된 Motion JPEG2000 부호화기를 FPGA를 타겟으로 구현하였다. JPEG2000의 주요 구성요소인 리프팅-기반의 DWT(Discrete Wavelet Transform)와 EBCOT(Embedded Block Coding with Optimized Truncation)의 Tier 1을 하드웨어로 구현하였고, Tier 2과정은 소프트웨어로 구현하였다. 디지털 시네마를 위해 입력 영상의 크기(tile size)는 최대 $1024\times1024$까지의 고해상도를 지원할 수 있도록 하였고, 실시간성을 보장하기 위해 3개의 엔트로피 부호화기를 사용하였다. Verilog-HDL을 이용하여 하드웨어로 구현했을 경우 Altera사의 Stratix EP1S80에서 32,470 LE (logic element)에 해당하는 자원을 사용하면서 FPGA에 사상되었고, 150Mhz의 주파수에서 안정적으로 동작하였다.

In the paper, a Motion JPEG2000 coder which has been set as the standard for image compression by the Digital Cinema Initiatives (DCI), an organization composed of major movie studios was implemented into a target FPGA. The DWT (Discrete Wavelet Transform) based on lifting and the Tier 1 of EBCOT (Embedded Block Coding with Optimized Truncation) which are major functional modules of the JPEG2000 were setup with dedicated hardware. The Tier 2 process was implemented in software. For digital cinema the tile-size was set to support $1024\times1024$ pixels. To ensure the real-time operations, three entropy encoders were used. When Verilog-HDL was used for hardware, resources of 32,470 LEs in Altera's Stratix EP1S80 were used, and the hardware worked stably at the frequency of 150Mhz.

키워드

참고문헌

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