JSTS:Journal of Semiconductor Technology and Science

  • 제7권2호
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  • Pages.76-81
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  • 2007
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

  • Choi, Byung-Kil (Dept. of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Park, Ki-Heung (Dept. of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Han, Kyoung-Rok (Dept. of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Kim, Young-Min (Dept. of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Lee, Jong-Ho (Dept. of Electronic and Electrical Engineering, Kyungpook National University)
  • 발행 : 2007.06.30
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초록

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

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참고문헌

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