References
- M. S. Suzuoki et al., 'A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder,' IEEE Journal of Solid-State Circuits, Vol.34, pp.1608-1618, Nov., 1999 https://doi.org/10.1109/4.799870
- K. Akeley, 'RealityEngine graphics,' In Proceedings of SIGGRAPH '93, pp.109-116, Aug., 1993 https://doi.org/10.1145/166117.166131
- J. S. Montrym, D. R. Baum, D. L. Dignam, and C. J. Migdal, 'InfinityRieality: A real-time graphics system,' Proceedings of SIGGRAPH '97, pp.293 - 302, Aug., 1997 https://doi.org/10.1145/258734.258871
- M. Deering and D. Naegle, 'The SAGE Architecture,' In Proceeddings of SIGGRAPH 2002, pp.683-692, July. 2002 https://doi.org/10.1145/566570.566638
- G. Humphreys, M.Eldridge, I. Buck, G. Stoll, M. Everett and P. Hanrahan, 'WireGL: A Scalable graphics system for clusters,' In Proceedings of SIGGRAPH 2001, pp.129-140, Aug., 2001 https://doi.org/10.1145/383259.383272
- A. K. Khan et al., 'A 150-MHz graphics rendering processor with 256-Mb embedded DRAM,' IEEE Journal of Solid State Circuits, Vol. 36, No.11, pp.1775-1783, Nov., 2001 https://doi.org/10.1109/4.962301
- S. Molnar, M. Cox, M. Ellsworth, and H. Fuchs, 'A sorting classification of parallel rendering,' IEEE Computer Graphics and Applications, Vol.14, No.4, pp.23-32, July, 1994 https://doi.org/10.1109/38.291528
- A. Wolfe and D. B. Noonburg, 'A superscalar 3D graphics engine,' In Proceedings of MICRO 32, pp.50-61, 1999 https://doi.org/10.1109/MICRO.1999.809443
- F. D. Michael, A. S. Stephen, and G. L. Michael, 'FBRAM: A new form memory optimized for 3D Graphics,' In Proceedings of SIGGRAPH '94, pp.167-174, 1994 https://doi.org/10.1145/192161.192194
- K. Inoue, H. Nakamura, and H. Kawai, 'A 10b Frame buffer memory with Z-compare and A-bending units,' IEEE Journal of Solid-State Circuits, Vol.30, No.12, pp.1563-1568, Dec., 1995 https://doi.org/10.1109/4.482207
- A. Kugler, 'The setup for triangle rasterization,' 11th Eurographics Workshop on Computer Graphics Hardware, pp.49-58, Aug., 1996
- Z. S. Hakura and A. Gupta, 'The design and analysis of a cache architecture for texture mapping,' In Proceedings of the 24thInternational Symposium on Computer Architecture, pp.108-120, June, 1997 https://doi.org/10.1145/264107.264152
- H. Igehy, M. Eldridge, and K. Proudfoot, 'Prefetching in a texture cache architecture,' In Proceedings of 1998 SIGGRAPH/Eurographics Workshop on Graphics Hardware, pp.133-142, August, 1998 https://doi.org/10.1145/285305.285321
- J. McCormack, R. McNamara, C. Gianos, L. Seiler, N. P. Jouppi, K. Correl, T. Dutton, and J. Zurawski, 'Neon: a (big) (fast) single-chip 3D workstation graphics accelerator,' Research Report 98/1, Western Research Laboratory, Compaq Corporation, Aug., 1998 (revised July 1999)
- L. Garber, 'The wild world of 3D graphics chips,' IEEE Computer, Vol.33, No.9, pp.12 - 16, Sept., 2000 https://doi.org/10.1109/MC.2000.868692
- Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, and Sung-Bong Yang, 'An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors,' IEEE Transactions on Computers, Vol.52, No.11, pp.1501-1508, Nov., 2003 https://doi.org/10.1109/TC.2003.1244948
- M. Woo, J. Neider, T. Davis, and D. Shreiner, OpenGL programming guide, Addison-Wesley, Third edition, 1999
- R. Bar-Yehuda and C. Gotsman, 'Time/space tradoffs for polygon mesh rendering,' ACM Transactions on graphics, Vol.15, No.2, pp.141-152, 1996 https://doi.org/10.1145/234972.234976
- Kai Hwang, Advanced computer architecture: parallelism, scalability, programmability, McGraw Hill, 1993
- M. D. Hill, J. R. Larus, A. R. Lebeck, M. Talluri, and D. A. Wood, 'Wisconsin architectural research tool set,' ACM SIGARCH Computer Architecture News, Vol.21, pp.8-10, Sep., 1993 https://doi.org/10.1145/165496.165500
- D. A. Patterson and J. L. Hennessy, Computer organization & design: The hardware/software interface, Morgan Kaufmann Publisher Inc., Second edition, 1998
- http://www.spec.org/gpc/opc.static/opcview70.html