JSTS:Journal of Semiconductor Technology and Science

  • 제6권4호
  • /
  • Pages.264-269
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  • 2006
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

A 0.12GHz-1.4GHz DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18um CMOS Process

  • Chi, Hyung-Joon (Dept. EE, Pohang University of Science and Technology) ;
  • Lee, Jae-Seung (Dept. EE, Pohang University of Science and Technology) ;
  • Sim, Jae-Yoon (Dept. EE, Pohang University of Science and Technology) ;
  • Park, Hong-June (Dept. EE, Pohang University of Science and Technology)
  • 발행 : 2006.12.31
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초록

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

키워드

참고문헌

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