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Gate Workfunction Optimization of a 32 nm Metal Gate MOSFET for Low Power Applications

  • Oh Yong-Ho (Advanced Nan-Tech. Development Division at Dongbu Electronics) ;
  • Kim Young-Min (HMED Lab. Dept. of Electrical, Information and Control Engineering, Hongik University)
  • Published : 2006.06.01

Abstract

The feasibility of a midgap metal gate is investigated for a 32 nm MOSFET for low power applications. The midgap metal gate MOSFET is found to deliver $I_{on}$ as high as a bandedge gate if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in the ITRS roadmap. A process simulation is also run to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. Based on the simulated result, it is found that any subsequent thermal process should be tightly controlled to retain transistor performance, which is achieved using the retrograde doping profile. Also, the bandedge gate MOSFET is determined be more vulnerable to the subsequent thermal processes than the midgap gate MOSFET. A guideline for gate workfunction $(\Phi_m)$ is suggested for the 32 nm MOSFET.

Keywords

References

  1. Semiconductor Industry Association, 'The International Technology Roadmap for Semiconductor 2003'
  2. Kingsuk, Maitra, and Veena, Misra, 'A Simulation Study to Evaluate the Feasibility of Midgap Workfunction Metal Gate in 25 nm Bulk CMOS', IEEE Electron Device Letters, Vol. 24, No. 11, pp. 707-709, November 2003 https://doi.org/10.1109/LED.2003.819267
  3. Indranil De, et al., 'Impact of gate workfunction on device performance at the 50 nm technology node', Solid-State Electronics, Vol. 44 (2000), pp. 1077- 1080 https://doi.org/10.1016/S0038-1101(99)00323-8
  4. Hon-sum Philip Wong, et al., 'Nanoscale CMOS', Proceedings of the IEEE, Vol. 87, No. 4, pp. 537-570, April 1999 https://doi.org/10.1109/5.752515
  5. Tseng, H.-H, et al., 'ALD $Hf0_2$ using heavy water $(D_2O)$ for improved MOSFET stability', IEDM Tech. Dig. pp. 83-86,2003
  6. Lee, J.C, et al., 'High-k dielectrics and MOSFET characteristics', IEDM Tech. Dig. 2003, pp. 95-98
  7. JaeHoon Lee, et al, 'Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS', IEDM Tech. Dig. pp. 323-326,2003
  8. F.Ootsuka, et al., 'Ultra-Low Thermal Budget CMOS Process for 65 nm-node Low Operation-Power Applications', IEDM Tech. Dig. pp. 647-650,2002
  9. Kim. Y.W, et al., '50 nm gate length technology with 9-layer Cu interconnects for 90 nm node SoC applications', IEDM Tech. Dig. pp. 69-72, 2002
  10. Michael Y. Kwong, et al., 'Impact of Lateral SourceIDrain Abruptness on Device Performance', IEEE Transacts on Electron Devices, Vol. 49, No. 11, pp. 1882-1890, November 2002 https://doi.org/10.1109/TED.2002.806790
  11. Yuan Taur, 'MOSFET Channel Length: Extraction and Interpretation', IEEE Transacts on Electron Devices, Vol. 47, No. 1, pp. 160-170, January 2000 https://doi.org/10.1109/16.817582

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