• Journal of Electrical Engineering and Technology
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• 제1권2호
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• pp.237-240
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• 2006

The feasibility of a midgap metal gate is investigated for a 32 nm MOSFET for low power applications. The midgap metal gate MOSFET is found to deliver $I_{on}$ as high as a bandedge gate if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in the ITRS roadmap. A process simulation is also run to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. Based on the simulated result, it is found that any subsequent thermal process should be tightly controlled to retain transistor performance, which is achieved using the retrograde doping profile. Also, the bandedge gate MOSFET is determined be more vulnerable to the subsequent thermal processes than the midgap gate MOSFET. A guideline for gate workfunction $(\Phi_m)$ is suggested for the 32 nm MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.