대한전기학회논문지:전력기술부문A (The Transactions of the Korean Institute of Electrical Engineers A)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

VHDL을 이용한 동기탈조 검출 알고리즘 구현에 관한 연구

A Study on Implementation of Out-of-Step Detection Algorithm using VHDL

  • 김철환 (성균관대학교 정보통신공학부) ;
  • 권오상 (성균관대학교 정보통신공학부)
  • 발행 : 2006.05.01
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⟨ 이전 논문 다음 논문 ⟩

초록

In a power system, an out-of-step condition causes a variety of risk such as serious damage to system elements, tripping of loads and generators, mal-operation of relays, etc. Therefore, it is very important to detect the out-of- step condition and take a proper measure. This paper presents a study on implementation of out-of-step detection algorithm using VHDL(Very high speed Hardware Description Language). The structure of out-of-step detection algorithm is analyzed for development of out-of-step detection relay on the FPGA(Field Programmable Gate Array). The out-of-step algorithm is separated to 4 parts: DFT IP, complex power calculation IP, out-of-step detection IP, control unit. Each parts are developed and simulated by using VHDL.

키워드

참고문헌

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