대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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새로운 BEOL 공정을 이용한 NBTI 수명시간 개선

Improvement of NBTI Lifetime Utilizing Optimized BEOL Process Flow

  • Ho Won-Joon (Dept. of Electronics Engineering, Chungnam National University) ;
  • Han In-Shik (Dept. of Electronics Engineering, Chungnam National University) ;
  • Lee Hi-Deok (Dept. of Electronics Engineering, Chungnam National University)
  • 발행 : 2006.03.01
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초록

본 논문에서는 NBTI 특성 개선을 위한 새로운 BEOL 공정을 제안하였다. 우선 BEOL의 마지막 공정인 수소 금속소결 열처리 공정, 보호막 공정 등이 NBTI에 많은 영향을 끼침을 분석하였다 이를 바탕으로 수소 금속소결 대신 질소 금속소결 공정을 적용하고 보호막 층, 특히 PE-SiN 증착 전에 질소 금속소결공정을 실시하여 NBTI 수명시간을 개선하였다. 제안한 방법을 적용하여도 소자 특성이나 NMOS의 HC 특성이 열화 되지 않음을 분석하여 실제 소자에 적용될 수 있음을 증명하였다.

The dependence of NBTI lifetime on the BEOL processes such as sintering gas type and passivation layer has been characterized in depth. Then, optimized BEOL process scheme is proposed to improve NBTI lifetime. NBTI showed degradation due to the plasma enhanced nitride (PE-SiN) passivation film and $H_2$ sintering anneal. Then, new process scheme of $N_2$ annealing instead of $H_2$ annealing prior to PE-SiN deposition is proposed. The proposed BEOL process flow showed that NBTI lifetime can be improved a lot without degradation of device performance and NMOS hot carrier reliability.

키워드

참고문헌

  1. D.K. Schroder and J.A. Babcock, 'Negative bias temperature instability : Road to cross in deep submicron silicon semiconductor manufacturing', J. Appl, Phys., Vol. 94, No.1, p.1-18, July 2003 https://doi.org/10.1063/1.1567461
  2. N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C.T. Liu, R.C. Keller and T. Horiuchi, 'NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-um gate CMOS generation', Symp. on VLSI Technology, p.92-93, 2000
  3. E. Morifuji, T. Kumamori, M. Muta, K. Suzuki, M.S. Krishnan, T. Brozek, X. Li, W. Asano, M. Nishigori, N. Yanagiya, S. Yamada, K. Miyamoto, T. Noguchi and M. Kakumu, 'New guideline for hydrogen treatment in advanced system LSI', Symp. on VLSI Technology, p.218-219, 2002 https://doi.org/10.1109/VLSIT.2002.1015459
  4. A. Suzuki, K. Tabuchi, H. Kimura, T. Hasegawa and S. Kadomura, 'A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability(NBTI) in p-MOSFETs with ultra-thin gate oxide', Symp, on VLSI Technology, p.216-217, 2002 https://doi.org/10.1109/VLSIT.2002.1015458
  5. S. Wolf, 'Silicon Processing for the VLSI Era The submicron MOSFET', Vol. 3, Chap. 9, p.642-647, Lattice Press, Sunset Beach, CA, 1995
  6. D.Y.C. Lie, J. Yota, W. Xia, A.B. Joshi, R.A. Williams, R. Zwingman, L. Chung and D.L. Kwong, 'New experimental findings on process-induced hot-carrier degradation of deep-submicron N-MOSFETs', Proc. Intl. Reliability Physics Symp., p.362-369, 1999 https://doi.org/10.1109/RELPHY.1999.761640
  7. S. Chetlur, S. Sen, E. Harris, H. Vaidya, I. Kizilyalli, R. Gregor and B. Harding, 'Influence of passivation anneal position on metal coverage dependent mismatch and hot carrier reliability', Proceedings of 7th IPFA, p.21-24, 1999 https://doi.org/10.1109/IPFA.1999.791266
  8. F.-C. Hsu, J. Hui,and K. Y. Chiu, 'Effect of final annealing on hot-electron-induced MOSFET degradation', IEEE Electron Dev. Lett., Vol. 6, No.7, p.369-371, July 1985 https://doi.org/10.1109/EDL.1985.26157
  9. J. Mitsuhashi, S. Nakao, T. Matsukawa, 'Mechanical stress and hydrogen effects on hot carrier injection', IEDM, p.386-389, 1986