Super Junction LDMOS with N-Buffer Layer

N 버퍽층을 갖는 수퍼접합 LDMOS

  • 박일용 (토론토대 전기 및 컴퓨터공학과)
  • Published : 2006.02.01

Abstract

A CMOS compatible Super Junction LDMOS (SJ-LDMOS) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and P-substrate to achieve global charge balance between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on-resistance, and reduced sensitivity to doping imbalance in the pillars.

Keywords

References

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