A Simulation Study for Analyzing an on-Demand Semiconductor Wafer Process

주문형 반도체 웨이퍼 공정분석을 위한 시뮬레이션 연구

  • Kim, Ki-Young (Logistics Program of International Relations Division, Dongseo University) ;
  • Lee, Jung-Ho (Department of Industrial Engineering, Pusan National University) ;
  • Kang, Chang-Ho (Department of Industrial Engineering, Pusan National University) ;
  • Kim, Kap-Hwan (Department of Industrial Engineering, Pusan National University)
  • 김기영 (동서대학교 국제관계학부국제물류) ;
  • 이정호 (부산대학교 산업공학과) ;
  • 강창호 (부산대학교 산업공학과) ;
  • 김갑환 (부산대학교 산업공학과)
  • Received : 2003.10.31
  • Accepted : 2005.01.20
  • Published : 2005.03.31

Abstract

This paper introduces a simulation model which is based on the process analysis of a semiconductor company. The objective of the simulation modelis not only to estimate the overall performancesof the company but also to evaluate the performances of various operation rules for shop floor control. First, in order to develop the simulation model, a time study is performed for each process after analyzing the processes for the company. Second, by using ARENA, a simulation model is constructed based on the process analysis and the time study. After the simulation model is tested and run, its results are discussed.

Keywords

References

  1. Dabbas, R. M.(2001), H. N. Chen,j. W. Fowler and D. Shunk, A Combined Dispatching Criteria Approach to Scheduling Semiconductor Manufacruring System, Computers & lndustrial Engineering, 39, 307-324 https://doi.org/10.1016/S0360-8352(01)00008-0
  2. Huang, M.(1998), D. Wang, W H. Ip, Simulation Study of CONWIP for a Cold Rolling Plant, Int. J. Production Economics, 54,257-266 https://doi.org/10.1016/S0925-5273(97)00152-7
  3. Kang, J.(1996), A Method for Target Scheduling of Semiconductor Wafer Fabfrication Based on Event-Based Optimization Modeling and Discrete Event Simulation, Ph.D, thesis, Universiry of California, Berkeley
  4. Lee, Y. S.(1997), S. y. Kim, S. H. Yea and B. K. Kim, Production Planning in Semiconductor Wafer Fab Considering Variable Cycle Times, Computer ind. Engng, 33(3-4), 713-716 https://doi.org/10.1016/S0360-8352(97)00229-5
  5. Lin, C Y,(1996), Shop Floor Scheduling of Semiconductor Wafer Fabricarion Using Real-Time Feedback Control and Prediction, Ph,D, thesis, University of California, Berkeley
  6. Shen, Y(1997), Stochastic Wafer Fabrication Scheduling, PhD. thesis, University of California, Berkeley
  7. Sivakumar, A. I. and C S. Chong(2001), A Simulation based Analysis of Cycle Time Distribution, and Throughput in Semiconductor Backend Manufacturing, Computers in Industry, 45, 59-78 https://doi.org/10.1016/S0166-3615(01)00081-1
  8. Sloan, T. W,(1998), Scheduling Semiconductor Wafer Manufacturing Using In-line Equipment Condition and Yield Information, Ph,D, thesis, University of California, Berkeley
  9. Sung, C S. and Y. L Choung(2000), Minimizing Makespan on a Single Burn-in Oven in Semiconductor Manufacturing, European Journal of Operational Research, 120, 559- 574 https://doi.org/10.1016/S0377-2217(98)00391-9
  10. Vargas-Villamil, F. D. and D. E, Rivera(2000), Multilayer Optimizarion and Scheduling Using Model Predictive Control: Application to Reentrant Semiconductor Manufacmring lines, Computers and Chemical Engineering, 24, 2009-2021 https://doi.org/10.1016/S0098-1354(00)00598-6