Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Efficient ACS Architecture for radix-4 Viterbi Decoder

Radix-4 비터비 디코더를 위한 효율적인 ACS 구조

  • Published : 2005.01.01
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Abstract

The Viterbi decoder which is used for the forward error correction(FEC) is a crucial component for successful modern communication systems. As modern communication speed rapidly high, the development of high speed communication module is important. However, since the feedback loop in ACS operation, high speed of Viterbi decoder is very difficult. In this paper, we propose an area reduced, high speed ACS Architecture of Viterbi decoder based on the radix-4 architecture. The area is reduced by rearranging the ACS operations, and the speed is improved by retiming of path metric memory. The proposed ACS architecture of Viterbi decoder is implemented in VHDL and synthesized in Xilinx ISE 6.2i. The area-time product of the proposed architecture is improved by 11% compared to that of the previous high speed radix-4 ACS architecture.

비터비 디코더는 통신 시스템에서 가장 핵심적인 부분 중의 하나로써 순방향 오류 정정을 위해 사용된다. 통신 속도의 고속화가 진행됨에 따라 고속에서 동작할 수 있는 통신 모듈의 개발이 점차 중요해지고 있다. 비터비 디코더는 궤환구조를 갖는 ACS 연산의 특성상 고속화가 매우 어렵다. 본 논문에서는 비터비 디코더의 고속화와 면적을 모두 고려한 효율적인 radix-4 ACS 구조를 제안하였다. 비터비 디코더의 ACS 연산을 재 정렬하여 면적을 절약하였고 경로 메트릭 메모리를 retiming하여 디코더의 속도를 개선하였다. 제안된 ACS 구조는 VHDL로 구현되었고 Xilinx의 ISE 6.2i에서 합성되었다. 실험을 통해서 제안된 구조의 AT product가 기존의 고속 radix-4 ACS 구조보다 11% 개선된 것을 확인할 수 있었다.

Keywords

References

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