A Cost-effective Control Flow Checking using Loop Detection and Prediction

루프 검출 및 예측 방법을 적용한 비용 효율적인 실시간 분기 흐름 검사 기법

  • Kim Gunbae (Yonsei University, Department of Electrical and Electronic Engineering) ;
  • Ahn Jin-Ho (Yonsei University, Department of Electrical and Electronic Engineering) ;
  • Kang Sungho (Yonsei University, Department of Electrical and Electronic Engineering)
  • 김근배 (연세대학교 전기전자공학과) ;
  • 안진호 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2005.12.01

Abstract

Recently, concurrent error detection for the processor becomes important. But it imposes too much overhead to adopt concurrent error detection capability on the system. In this paper, a new approach to resolve the problems of concurrent error detection is proposed. A loop detection scheme is introduced to reduce the repetitive loop iteration and memory access. To reduce the memory overheat an offset to calculate the target address of branching node is proposed. Performance evaluation shows that the new architecture has lower memory overhead and frequency of memory access than previous works. In addition, the new architecture provides the same error coverage and requires nearly constant memory size regardless of the size of the application program. Consequently, the proposed architecture can be used as an cost effective method to detect control flow errors in the commercial on the shelf products.

최근의 저 전력 컴퓨터 시스템은 내장 프로세서의 성능 향상과 공정 기술의 발전을 통한 디바이스 크기 감소로 인해 전압 변동, 커플링 효과 등으로 인한 SEU(single event upset)로 모델링 되는 천이고장으로 인한 예기치 못한 동작 중 에러 발생가능성이 매우 높아지고 있다. 제안하는 방식은 프로세서가 처리하는 프로그램 분기 흐름상에서 에러를 검출하는 효과적인 watchdog 프로세서 구조로서, 기존 방식이 가지는 오버헤드를 줄이면서 프로그램 내부에서 빈번히 발생되는 루프를 매번 검사할 때, 동일한 동작을 watchdog 프로세서가 반복함으로써 생기는 비효율적인 메모리 접근, 버스 점유 경쟁등과 같은 추가적인 시스템 수준의 오버헤드를 줄이는 새로운 방법을 제안하였다. 본 논문은 기존의 실시간 분기 및 제어 흐름 연구에서는 다루지 않았던 루프 검출 및 예측 기능을 추가함으로써 실제 시스템 적용에 보다 적합한 비용 효율적인 구조를 제안하고 있다.

Keywords

References

  1. A. Messer, P. Bernadat, G. Fu, D. Chen, Z. Dimitrijevic, D. Lie, D. D. Mannaru, A. Riska, D. Milojicic, 'Susceptibility of Modern Systems and Software to Soft Errors,' Technical Report, Hewlett Packard Lab, 2001
  2. U. Gunneflo, J. Karlsson, J. Torin. 'Evaluation of error detection schemes using fault injection by heavy-ion radiation,' Proceedings of 19th International Symposium on Fault-Tolerant Computing, pp. 340-347, 1989 https://doi.org/10.1109/FTCS.1989.105590
  3. A. Mahmood and E. J. McCluskey, 'Concurrent Error Detection Using Watchdog Processors - A Survey,' IEEE Transactions on Computers, Vol. 37, pp. 160-174, 1988 https://doi.org/10.1109/12.2145
  4. N. R. Saxena and E. J. McCluskey, 'Control-flow Checking Using Watchdog Assists and Extended Precision Checksums,' IEEE Transactions on Computers, Vol. 39, pp. 554-559, 1990 https://doi.org/10.1109/12.54849
  5. P. Shen and M. A. Schuette, 'On-line Self-monitoring Using Signatured Instruction Streams,' Proceedings of International Test Conference, pp. 275-282, 1982
  6. N. Oh, P. P. Shirvani, E. J. McCluskey, 'Control-Flow Checking by Software Signatures,' IEEE Transactions on Reliability, Vol. 51, pp. 111-122, 2002 https://doi.org/10.1109/24.994926
  7. D. J. Lu, 'Watchdog Processor and Structural Integrity Checking,' IEEE Transactions on Computers, Vol 31, pp. 681-685, 1982 https://doi.org/10.1109/TC.1982.1676066
  8. Ohlsson and M. Rimen, 'Implicit Signature Checking,' Proceedings of 25th International Symposium on Fault-Tolerant Computing, pp. 218-227, 1995 https://doi.org/10.1109/FTCS.1995.466976
  9. Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray, 'Low-Cost On-Line Fault Detection Using Control Flow Assertions,' Proceedings of 9th IEEE International On-Line Testing Symposium, pp137-143, 2003 https://doi.org/10.1109/OLT.2003.1214380
  10. G. Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis, 'Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores,' Proceedings of 9th IEEE International On-Line Testing Symposium, pp. 149-154, 2003 https://doi.org/10.1109/OLT.2003.1214382
  11. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, 'A Watchdog Processor to Detect Data and Control Flow Errors,' Proceedings of 9th IEEE International On-Line Testing Symposium, pp. 144-148, 2003 https://doi.org/10.1109/OLT.2003.1214381
  12. M. Namjoo, E. J. McCluskey, 'Watchdog Processor and Capability Checking,' Proceedings of 25th International Symposium On Fault-Tolerant Computing, pp. 94-97, 1995
  13. T. Michel, R. Leveugle, G. Saucier, 'A New Approach to Control Flow Checking without Program Modification,' Proceedings of 21st International Symposium on Fault-Tolerant Computing, pp. 334-341, 1991 https://doi.org/10.1109/FTCS.1991.146682
  14. M. R. de Alba and D. R. Kaeli, 'Runtime Predictability of Loops,' Proceedings of 4th IEEE Workshop on Workload Characterization, pp. 91-98, 2001 https://doi.org/10.1109/WWC.2001.20
  15. M. Kobayashi, 'Dynamic Characteristics of Loops,' IEEE Transactions on Computers, Vol 32, pp. 125-132, 1984
  16. T. Sherwood and B. Calder, 'Loop Termination Prediction,' Proceedings of the 3rd International Symposium on High Performance Computing, pp. 73-87, 2000 https://doi.org/10.1007/3-540-39999-2_8