Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A Design of CMOS Transceiver for noncoherent UWB Communication system

비동기방식 UWB통신용 CMOS 아날로그 송수신단의 설계

  • Park, Jung-Wan (Department of Electronic Engineering, Soongsil University) ;
  • Moon, Yong (Department of Electronic Engineering, Soongsil University) ;
  • Choi, Sung-Soo (Power Telecommunication Network Group, Korea Electrotechnology Research Institute)
  • Published : 2005.12.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

이 논문에서는 비동기 OOK 방식의 UWB 시스템에서 사용할 수 있는 아날로그 송수신단을 설계하였다. 설계한 송수신단은 $0.18{\mu}m$ CMOS 공정을 사용하여 구현 하였으며, SPICE 모의실험과 측정을 통하여 검증을 하였다. 제안된 송수신단은 병렬기, 아날로그-디지털 변환기, 클럭 생성기, 위상고정루프(PLL), 그리고 임펄스 생성기 등으로 이루어져 있다. 동작속도는 125MHz로 동작하는 아날로그-디지털 변환기 8개를 병렬로 연결하여 1Gbps의 속도를 얻으며, 8개의 병렬화된 출력을 얻는다. 이 출력은 D-F/F에 의해 동기화되고, 이 동기화된 출력들은 기저대역으로 전달된다. 임펄스 생성기는 CMOS 디지털 게이트로 이루어져 있으며, 약 1ns의 폭을 가지는 임펄스를 생성한다. 본 논문에서 제안된 송수신단의 모의실험 결과와 측정결과는 저전력 UWB 시스템의 구현이 가능하고, 병렬화를 택해서 높은 데이터 전송률을 얻을 수 있다는 가능성을 보여준다.

Keywords

References

  1. Federal Communications Commission, Revision of Part 15 of the Commission's Rules Regarding Ultra- Wideband Transmission, ET Pocket 98-153, April 2002
  2. http://www.ieee802.org/l5/pub/TG3a.html
  3. I. Immoreev and A. Sudakov, 'Ultra-wideband interference resistant system for secure radio communi- cation with high data rate,' Proc. IEEE Int'l Conf. Circuits & Syst. for Commun. (ICCSC 2002), pp. 230-233, St. Petersburg, Russia, June 2002
  4. M. Z. Win and R. A. Scholtz, 'Impulse radio: How it works,' IEEE Communication Letter, vol. 2, no. 2, pp. 36-38, February 1999 https://doi.org/10.1109/4234.660796
  5. S. Y. Lee, 'Design and Analysis of Ultra-Wide Bandwidth Impulse Radio Receiver,' Ph. D Dissertation, University of Southern California, August 2002
  6. I. D. O'Donnell, M. S. W. Chen, S. B. T. Wang, and R. W. Brodersen, 'An integrated, low power, ultra-wide band transceiver architecture for low-rate, indoor wireless systems,' Proc. IEEE Workshop Wireless Communication & Networking, Pasadena, USA, September 2002
  7. Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits - Theory and Design, IEEE Press, 1996
  8. M. Horowitz, A. Chan, J. Cobrunson, J. Gasbarro, T. Lee, W. Leung, W. Richardson, T. Thrush, Y. Fujii, 'PLL design for a 500 MB/s interface,' Digest of Technical Papers. 40th ISSCC, pp.160-161, 1993 https://doi.org/10.1109/ISSCC.1993.280015
  9. R. Jacob Baker, E. Boyce David, CMOS: Circuit Design, Layout, and Simulation, Williy-IEEE, August 1997
  10. Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, McGRAW-HILL, Third Edition, 2003
  11. I. J. Immeoreev and A. A. Sudakov, 'Ultra-Wideband Communication System with High Data Rate,' Ultrawideband and Ultrashort Impulse Signals (UWBUSIS'02), Oct. 2002