Low-Power Multiplier Using Input Data Partition

입력 데이터 분할을 이용한 저전력 부스 곱셈기 설계

  • Published : 2005.11.01

Abstract

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

본 논문에서는 곱셈을 수행할 때 발생되는 스위칭 을을 줄이는 방식의 저전력 부스 곱셈기를 제안한다. radix-4 부스 알고리즘 (radix-4 Booth algorithm)은 입력에서 연속되는 3비트가 0이나 1의 같은 값을 가지게 되면, 부스 인코딩 결과로서 0을 발생시키는 특성을 가지고 있다. 따라서 곱셈기의 두 입력 중 더 작은 활성영역을 갖는 입력을 승수로 사용할 때 부분 곱셈결과가 0이 될 확률이 높다. 제안된 곱셈기는 곱셈식을 본래의 곱셈 입력 비트보다 더 작은 비트를 갖는 여러 개의 곱셈식으로 분할한 후, 각각의 곱셈들을 독립적으로 계산하여 각각의 곱셈의 결과를 더하여 최종적인 결과를 얻는다. 따라서 곱셈의 두 입력간의 교환율은 기존의 곱셈기보다 더 높아지게 된다. 이는 제안된 곱셈기의 부스 인코딩 결과가 0이 되는 확률이 기존의 곱셈기보다 더 높은 저전력 곱셈기를 구현할 수 있음을 의미한다. 제안된 곱셈기는 기존의 부스 곱셈기보다 최대 $20\%$ 정도의 소모전력이 감소됨을 확인하였다.

Keywords

References

  1. Chang-Young Han, Hyoung-Joon Park and Lee-Sup Kim, 'Alow-power array multiplier using separated multiplication technique,' Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, Volume: 48 Issue: 9, Sep 2001 Page(s): 866-871
  2. C. Lemonds, 'A high throughput 16 by 16 bit multiplier for DSP cores,' IEEE International Symposium on Circuits and Systems, ISCAS, vol. 2, pp. 477-480. 1996
  3. Turner, R.H., Courtney, T. and Woods, R., 'Implementation of fixed DSP functions using the reduced coefficient multiplier, Acoustics, Speech, and Signal Processing,' 2001. proceedings. (ICASSP '01). 2001 IEEE International Conference on, volume: 2, 2001 Page(s): 881-884 vol.2
  4. Yiquan Wu and Zhaoda Zhu, 'The new real-multiplier FFT-j alforithms,' Aerospace and Electronics Conference, 1993. NAECON 1993., proceedings of the IEEE 1993 National, 24-28 May 1993, Page(s): 90-93 vol.1
  5. Yi-Wen Wu, Chen, O.T.-C and Ruey-Liang Ma, 'A low-power digital signal processor core by minirnizing inter-data switching activities,' Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on, Volume: 1, 2001 Page(s): 172-175 vol.1
  6. Paliouras, V., Karaginni, K. and Stouraitis, T. 'A low-complexity combinatorial RNS multiplier,' Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, Volume: 48 Issue: 7, Jul 2001 Page(s): 675-683
  7. Fayed, A.A and Bayoumi, M.A, 'A merged multiplier-accumulator for high speed signal processing applications,' Acoustics, Speech, and Signal Processing, 2002. Proceedings. (ICASSP '02). IEEE International Conference on, Volume: 3, 2002 Page(s): III-3212-III-3215 vol.3
  8. Kim, S. and Papaefthymiou, M.C., 'Reconfi-gurable low energy multiplier for multimedia system design,' VLSI, 2000. Proceedings. IEEE Computer Society Workshop on, 2000 Page(s): 129-134
  9. Bakalis, D., Kalligeros, E., Nikolos, D., Vergos, H.T. and Alexiou, G., 'Low power BIST for Wallace tree-based multipliers,' Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on, 2000 Page(s): 433-438
  10. Zhan Yu, Wasserman, L., and Willson, A.N., Jr., 'A painless way to reduce power dissipation by over 18% in 부스-encoded carry-save array multipliers for DSP,' Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on, 11-13 Oct. 2000, Page(s): 571-580
  11. Taekyoon Ahn and Kiyoung Choi, 'Dynamic operand interchange for low power,' Electronics Letters, Volume: 33 Issue: 25, 4 Dec. 1997, Page(s): 2118-2120 https://doi.org/10.1049/el:19971440
  12. Nan-Ying Shen and Chen, O.T.-C, 'Low-power multipliers by minimizing switching activities of partial products,' Circuits and Systems, 2000. ISCAS 2002. IEEE International symposium on, Volume: 4, 2002 Page(s): IV-93 IV-96 vol.4
  13. Madrid, P.E., Miller, B. and Swartzlander, E.E., Jr., 'Modified Booth algorithm for high radix multiplication,' Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, Page(s): 118-121