Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a high-speed DFE Equaliser of blind algorithm using Error Feedback

Error Feedback을 이용한 blind 알고리즘의 고속 DFE Equalizer의 설계

  • Published : 2005.08.01
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Abstract

This paper proposes a Decision Feedback Equalizer (DFT) with an error feedback filter for blind channel equalization. The proposed equalizer uses Least Mean Square(LMS) Algorithm and Multi-Modulus Algorithm (MMA), and has been designed for 64/256 QAM constellations. The existing MMA equalizer uses either two transversal filters or feedforward and feedback filers, while the proposed equalizer uses feedforward, feedback and error feedback filters to improve the channel adaptive performance and to reduce the number of taps. The proposed equalizer has been simulated using the $SPW^{TM}$ tool and it shows performance improvement. It has been modeled by VHDL and logic synthesis has been performed using the $0.25\;\mu m$ Faraday CMOS standard cell library. The total number of gates is about 190,000 gates. The proposed equalizer operates at 15 MHz. In addition, FPGA vertification has been performed using FPGA emulation board.

본 논문에서는 Blind 채널 등화를 위한 error feedback 필터를 갖는 Decision Feedback Equalizer(DFE) 구조의 등화기를 설계하였다. 제안하는 등화기는 Least Mean Square(LMS) 알고리즘과 Multi-Modulus Agorithm(MMA)을 이용하였으며 64/256 QAM을 위해 설계되었다. 기존의 MMA 등화기는 두개의 transversal 필터를 이용하거나 feedforward와 feedback 필터를 이용하는 반면에 제안하는 등화기는 feedforward와 feedback 그리고 error feedback 필터를 사용하여 채널 적응 성능을 향상시켰으며 탭 수를 감소시켰다. 제안하는 구조는 $SPW^{TM}$ 툴을 이용 시뮬레이션을 수행하여 성능을 개선시킬 수 있었다. 그리고 VHDL을 이용해 시뮬레이션을 수행하였으며 논리 합성은 0.25um 셀 라이브러리를 이용하였다. 설계한 등화기는 약 19만 게이트 수와 15MHz의 동작속도를 보였다 또한 FPGA 칩을 내장한 이뮬레이션 보드를 사용하여 성능 검증을 수행하였다.

Keywords

References

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