참고문헌
- Synopsys Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA. COSSAP User's Manual: VHDL Code Generation
- J. T. Buck, S. Ha, E. A. Lee and D. G. Messerschmitt. Ptolemy: A framework for simulating and prototyping heterogeneous systems. Int'l journal of Computer simulation, special issues on 'Simulation software development,' vol.4, pp. 155-182, April, 1994
- M. Ade, R. Lauwereins, and J. A. Peperstraete. Hardware-software codesign with GRAPE. IEEE Int'l Workshop on Rapid System Prototyping, pp. 40-47, June, 1995 https://doi.org/10.1109/IWRSP.1995.518569
- G. De Micheli. Synthesis and Optimization of Digital Circuits. New York, McGraw-Hill, Inc., 1994
- E. A. Lee and D. G. Messerschmitt. Synchronous data flow. Proc. of the IEEE, September, 1987
- H. Oh and S. Ha. Fractional rate dataflow model and efficient code synthesis for multimedia applications. ACM SIGPLAN Notice Vol. 37, pp. 12-17, July 2002 https://doi.org/10.1145/566225.513834
- H. Oh and S. Ha. Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints. International Workshop on Hardware/Software Codesign, pp. 133-138, May 2002 https://doi.org/10.1145/774789.774817
- P. Zepter and T. Groker and H. Meyr, Digital receiver design using VHDL generation from data flow graphs. Proceedings of the Design Automation Conference 1995 https://doi.org/10.1109/DAC.1995.250095
- J. Horstmannshoff and H. Meyr. Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs. International Symposium on System Synthesis, pp. 38-43, Nov, 1999 https://doi.org/10.1109/ISSS.1999.814258
- M. C. Williamson and E. A. Lee. Synthesis of parallel hardware implementations from synchronous dataflow graph specifications. In 30th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 1996 https://doi.org/10.1109/ACSSC.1996.599166
- Y.-L. Lin. Recent Devleopments in High-Level Synthesis. ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No.1, pp 2-21, Jan. 1997 https://doi.org/10.1145/250243.250245
- D. W. Knapp. Behavioral Synthesis: Digital System Design Using the Synopsys Behavioral Compiler. Prentice Hall, 1996
- L. Semeria, K. Sato, and G. De Micheli. Synthesis of Hardware Models in C With Pointers and Complex Data Structures. IEEE Transactions on VLSI Systems Vol. 9, pp. 743-756, Dec. 2001 https://doi.org/10.1109/92.974889
- L. Semeria and G. De Micheli. Resolution, Optimization, and Encoding of Pointer Variables for the Behavioral Synthesis from C. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol. 20, pp. 213-233, Feb. 2001 https://doi.org/10.1109/43.908442
- N. Vanspauwen, E. Barros, S. Cavalcante, and C. Valderrama. On the Importance, Problems and Solutions of Pointer Synthesis. 15th Symposium on Integrated Circuits and Systems Design, pp. 317-322, Sept. 2002 https://doi.org/10.1109/SBCCI.2002.1137677
-
F. Slomka, M. Dorfel, and R. Munzenberger. Generating Mixed Hardware/Software systems from SDL Specifications.
$9^{th}$ International Symposium on Hardware/Software Codesign, pp. 116-121, April 2001 https://doi.org/10.1109/HSC.2001.924661 - O. Bringmann, W. Rosenstiel, A. Muth, G. Farber, F. Slomka, and R. Hofmann. Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. IEEE Int'l Workshop on Rapid System Prototyping, pp. 114-119, June 1999 https://doi.org/10.1109/IWRSP.1999.779040
- J. Horstmannshoff, T. Grotker. and H. Meyr. Mapping multi-rate dataflow to complex RT level hardware models. In ASAP. IEEE, 1997
- J. Dalcolmo, R. Lauwereins, M. Ade. Code generation of data dominated DSP applications for FPGA targets. IEEE Int'l Workshop on Rapid System Prototyping, pp. 162-167, 1998 https://doi.org/10.1109/IWRSP.1998.676686
- G. Bilsen, M.Engels, R. Lauwereins and J. Peperstraete. Cycle-static dataflow. IEEE Transactions on Signal Processing Vol. 44, pp.397-408, Feb. 1996 https://doi.org/10.1109/78.485935
- H. Jung, K. Lee, and S. Ha. Efficient hardware controller synthesis for synchronous dataflow graph in system level design. IEEE Transactions on VLSI Systems Vol. 10, pp. 423-428, August 2002 https://doi.org/10.1109/TVLSI.2002.807765