대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Crosstalk과 정적 고장을 고려한 효과적인 연결선 테스트 알고리즘 및 BIST 구현

Efficient Interconnect Test Patterns and BIST Implementation for Crosstalk and Static Faults

  • 민병우 (한양대학교 컴퓨터공학과) ;
  • 이현빈 (한양대학교 컴퓨터공학과) ;
  • 송재훈 (한양대학교 컴퓨터공학과) ;
  • 박성주 (한양대학교 전자컴퓨터공학부)
  • Min Pyoungwo (Department of Computer Science ' Engineering, Hanyang University) ;
  • Yi Hyunbean (Department of Computer Science ' Engineering, Hanyang University) ;
  • Song Jaehoon (Department of Computer Science ' Engineering, Hanyang University) ;
  • Park Sungju (Department of Electronical Engineering Computer Science, Hanyang University)
  • 발행 : 2005.07.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 보드 또는 SoC 상에서 코아와 코아 사이의 연결선 고장 점검을 위한 효과적인 테스트 패턴 알고리즘과 테스트 패턴 생성기를 소개한다. 연결선 고장 모델 분석을 통해 crosstalk과 정적인 고장을 100$\%$ 점검할 수 있는 6n 패턴 알고리즘을 소개한다 보다 적은 4n+1 개의 패턴으로 100\$\%$에 가까운 고장 점검율을 얻으면서 crosstalk 뿐 아니라 정적고장의 검출 및 진단도 가능한 알고리즘을 제안하고, 효과적인 BIST구현 기술에 대하여 소개한다.

This paper presents effective test patterns and their BIST implementations for SoC and Board interconnects. Initially '6n'algorithm, where 'n' is the total number of interconnect nets, is introduced to completely detect and diagnose both static and crosstalk faults. Then, more economic 4n+1 algorithm is described to perfectly capture the crosstalk faults for the interconnect nets separated within a certain distance. It will be shown that both algorithms can be easily implemented as interconnect BIST hardwares with small area penalty than conventional LFSR.

키워드

참고문헌

  1. A. Hassan and J. Rajski and V.K. Agrawal, 'Testing and Diagnosis of Interconnects using Boundary Scan Architecture' Proceedings International Test Conference, pp.126-137. 1988 https://doi.org/10.1109/TEST.1988.207790
  2. W. T. Cheng, J. L. Lewandowski and E. Wu, 'Optimal Diagnostic Methods for Wiring Interconnects' IEEE Transactions on Computer-Aided Design, Vol 11, No.9, pp. 1161-1166, Sept. 1992 https://doi.org/10.1109/43.160002
  3. N. Jarwala and C.W. Yau, 'A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects' Test Conference, Proceedings, International, pp. 63-70, Aug. 1989 https://doi.org/10.1109/TEST.1989.82278
  4. Yongjoon Kim; Hyun-don Kim; Sungho Kang, 'A new maximal diagnosis algorithm for interconnect', Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume 12, Issue 5, pp. 532 - 537, May 2004 https://doi.org/10.1109/TVLSI.2004.826200
  5. Yi Zhao; Dey, S., 'Fault-coverage analysis techniques of interconnects crosstalk in chip', Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 22, pp. 770 - 782, June, 2003 https://doi.org/10.1109/TCAD.2003.811444
  6. M. Cuviello, S.Dey, X.Bai, and Y.Zhao, 'Fault modeling and simulation for crosstalk in system-on-chip interconnects', In Proc. Int. Conf. Computer-Aided Design, pages 297-303, Nov. 1999 https://doi.org/10.1109/ICCAD.1999.810665
  7. Xiaoliang Bai and S. Dey and J. Rajski, 'Self-test methodology for at-speed test of crosstalk in chip interconnects,' Design Automation Conference, Proceedings 2000. 37th, pp. 619 - 624, June 5-9, 2000
  8. K. Sekar and S. Dey, 'LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects,' VLSI Test Symposium, (VTS 2002). Proceedings 20th IEEE, pp. 417 - 422, 28 April- 2 May 2002 https://doi.org/10.1109/VTS.2002.1011174
  9. R. Pendurkar and A. Chatterjee and Y. Zorian, 'Switching activity generation with automated BIST synthesis for performance testing of interconnects,' Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume 20, pp. 1143 - 1158, Sept. 2001 https://doi.org/10.1109/43.945309
  10. Sirisaengtaksin and Sandeep K. Gupta 'Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology' Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian, 18-20 pp. 163 - 169, Nov. 2002