대한전기학회논문지:전기물성ㆍ응용부문C (The Transactions of the Korean Institute of Electrical Engineers C)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

낮은 Subthreshold 누설전류를 갖는 CMOS 논리회로

CMOS Logic Circuits with Lower Subthreshold Leakage Current

  • 송상헌 (중앙대학교 전자전기공학부)
  • 발행 : 2004.10.01
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초록

We propose a new method to reduce the subthreshold leakage current. By moving the operating point of OFF state MOSFETs through input-controlled voltage generators, logic circuits with much lower leakage current can be built with few extra components. SPICE simulation results for the new inverter show correct logic results without speed degradation compared to a conventional inverter.

키워드

참고문헌

  1. Itoh, K., Nakagome, Y., Kimura, S., and Watanabe, T.: 'Limitations and Challenges of Multigigabit DRAM Chip Design,' IEEE J. Solid-State Circuits, Vol. 32, pp. 624-634, May 1997 https://doi.org/10.1109/4.568820
  2. Moore, G. E.: 'Progress in digital integrated circuit,' IEDM Tech. Dig., p. 11, Dec. 1975
  3. See, for example, Lindert, N., Sugii, T., Tang, S., and Hu, C.: 'Dynamic Threshold Pass-Transistor Logic for Improved Delay at Low Power Supply Voltages,' IEEE J. Solid-State Circuits, vol. 34, pp. 85-89, Jan. 1999 https://doi.org/10.1109/4.736659
  4. Sakata, T., Itoh, K., Horiguchi, M., and Aoki, M.: 'Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's,' IEEE J. Solid-State Circuits, Vol. 29, pp. 761-769, Jul. 1994 https://doi.org/10.1109/4.303713
  5. Mutoh, S., Douseki, T., Matsuya, Y, Aoki, T., Shigematsu, S., and Yamada, J.: '1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,' IEEE J. Solid-State Circuits, vol. 30, pp, 847-854, Aug. 1995 https://doi.org/10.1109/4.400426
  6. Horiguchi, M., Sakata, T., and Itoh, K.: 'Switched-Source-Impedance CMOS Circuit For Low Standby Subthreshold Current Giga-Scale LSI s,' IEEE J. Solid-State Circuits, vol. 28, pp. 1131-1135, Nov. 1993 https://doi.org/10.1109/4.245593
  7. Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshoka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., and Sakurai, T.: 'A 0.9-V, 150-MHz, 10-mW, 4 $mm^2$, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme,' IEEE J. Solid-State Circuits, Vol. 31, pp. 1770-1779, Nov. 1996 https://doi.org/10.1109/JSSC.1996.542322
  8. Muller, R. S. and Kamins, T. I.: 'Device Electronics for Integrated Circuits,' 2nd Edition, Chap. 10, Wiley, 1986
  9. Troutman, R. R.: 'VLSI Limitations from Drain-Induced Barrier Lowering,' IEEE J. Solid-State Circuits, SC-14, p. 383, Apr. 1979 https://doi.org/10.1109/T-ED.1979.19449