낮은 Subthreshold 누설전류를 갖는 CMOS 논리회로

CMOS Logic Circuits with Lower Subthreshold Leakage Current

  • 송상헌 (중앙대학교 전자전기공학부)
  • 발행 : 2004.10.01

초록

We propose a new method to reduce the subthreshold leakage current. By moving the operating point of OFF state MOSFETs through input-controlled voltage generators, logic circuits with much lower leakage current can be built with few extra components. SPICE simulation results for the new inverter show correct logic results without speed degradation compared to a conventional inverter.

키워드

참고문헌

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