대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Data Weighted Averaging을 이용한 3차 멀티비트 Sigma-Delta 변조기

The Third-Order Multibit Sigma-Delta Modulator with Data Weighted Averaging

  • 김선홍 (전북대학교 전기공학과) ;
  • 최석우 (전북대학교 전자정보공학부) ;
  • 조성익 (전북대학교 전자정보공학부) ;
  • 김동용 (전북대학교 전저정보공학부)
  • 발행 : 2004.09.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 DWA(Data Weighted Averaging) 방식의 sigma-delta 변조기에서 피드백 지연시간을 최적화 할 수 있는 DWA 구조의 블록도 및 타이밍도를 제안한다. 변조기 설계를 위하여 MATLAB 모델링으로 적분기의 최적 계수를 설정한 후 변조기의 비이상성을 고려하여 완전 차동 SC 적분기, 피드백 DAC, 9-레벨 양자화기, DWA를 설계하였다. 각 블록을 이용하여 실현된 3차 멀티비트 sigma-delta 변조기는 0.35㎛ CMOS 공정으로 칩으로 제작하였고, 동작 특성은 1.2Vp-p 825kHz의 입력 신호, 샘플링 주파수 52.8MHz에서 75dB의 SNR과 74dB의 DR을 가진다.

This paper presents block and timing diagrams of the DWA(Data Weighted Averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the MATLAB modeling, the optimized coefficients of the integrators are obtained to design the modulator. The fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed third-order multibit modulator is fabricated in a 0.35${\mu}{\textrm}{m}$ CMOS process. The modulator achieves 75dB signal-to-noise ratio and 74dB dynamic range at 1.2Vp-p 825kHz input signal and 52.8MHE sampling frequency.

키워드

참고문헌

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