HVIA-GE: 기가비트 이더넷에 기반한 Virtual Interface Architecture의 하드웨어 구현

HVIA-GE: A Hardware Implementation of Virtual Interface Architecture Based On Gigabit Ethernet

  • 박세진 (부산대학교 컴퓨터공학과) ;
  • 정상화 (부산대학교 컴퓨터공학) ;
  • 윤인수 (부산대학교 컴퓨터공학과)
  • 발행 : 2004.06.01

초록

본 논문에서는 고성능 PC 클러스터 시스템을 위한 사용자 수준 인터페이스인 Virtual Interface Architecture(VIA)를 기가비트 이더넷을 기반으로 하여 하드웨어로 구현하였다. 기가비트 이더넷 상의 하드웨어 VIA (HVIA-GE)는 PCI 33MHz/32bit 버스 기반으로 하고, 물리적인 네트워크로는 고성능 클러스터 시스템 구축을 위해 기가비트 이더넷을 채용하였으며, FPGA를 사용하여 VIA 프로토콜 엔진을 구현하였다. 주소변환 및 Doorbell 메커니즘을 커널의 간섭 없이 하드웨어로 처리하도록 하였으며, 특히 효율적인 주소변환을 위해 ATT를 HVIA-GE 카드상의 SDRAM에 저장하고 VIA 프로토콜 엔진에서 직접 처리하도록 개발하였다. 이러한 구현의 결과로 송수신시에 발생하는 통신 오버헤드를 대폭 줄이게 되었으며, 최소 11.9${\mu}\textrm{s}$의 지연 시간, 최대 93.7MB/s의 대역폭을 얻을 수 있었다 HVIA-GE는 최소 지연시간에 있어서 기가비트 이더넷 상에서 VIA의 소프트웨어 구현 방식인 M-VIA에 비해 약 4.8배, 기가비트 이더넷상에서의 TCP/IP에 비해 약 9.9배 빠른 결과를 나타내었다. 또한, 최대 대역폭에 있어서는 M-VIA에 비해 약 50.4%, TCP/IP에 비해 약 65%의 성능향상을 가져왔다.

This paper presents the implementation and performance of the HVIA-GE card, which is a hardware implementation of the Virtual Interface Architecture (VIA) based on Gigabit Ethernet. The HVIA-GE card is a 32-bit/33MHz PCI adapter containing an FPGA for the VIA protocol engine and a Gigabit Ethernet chip set to construct a high performance physical network. HVIA-GE performs virtual-to-physical address translation, Doorbell, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the HVIA-GE card, and the VIA protocol engine efficiently controls the address translation process by directly accessing the ATT. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show the maximum bandwidth of 93.7MB/s and the minimum latency of 11.9${\mu}\textrm{s}$. In terms of minimum latency HVIA-GE performs 4.8 times and 9.9 times faster than M-VIA and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of HVIA-GE is 50.4% and 65% higher than M-VIA and TCP/IP respectively.

키워드

참고문헌

  1. T. von Eicken, D. E. Culler, S. C. Goldstein, and K. E. Schauser, 'Active Messages: A Mechanism for Integrated Communication and Computation,' 19th International Symposium on Computer Architecture, May 1992 https://doi.org/10.1145/139669.140382
  2. S. Pakin, M. Lauria, and A. Chien. 'High Performance Messaging on Workstations: Illinois Fast Messages(FM) for Myrinet,' Proc. of the Supercomputing'95, December 3-8, 1995 https://doi.org/10.1145/224170.224360
  3. T. von Eicken, A. Basu, V. Buch, and W. Vogels. 'U'-Net: A User-level Network Interface for Parallel and Distributed Computing,' Proc, of the 15th ACM Symposium on Operating Systems Principles(SOSP), Colorado, December 3-6, 1995 https://doi.org/10.1145/224056.224061
  4. Virtual Interface Architecture Specification. http://www.viarch.org/
  5. P. Bozeman and B. Saphir, 'A Modular High Performance implementation of the Virtual Interface Architecture,' Proc. Of the 2nd Extreme Linux Workshop, June 1999
  6. P. Buonadonna, A. Geweke, and D.E. Culler, 'An Implementation and Analysis of the Virtual Interface Architecture,' Proc. Of SC'98, Orlando, FL, Nov. 7-13, 1998 https://doi.org/10.1109/SC.1998.10052
  7. Emulex Corporation, Hardware-based (ASIC) implementation of the Virtual Interface standard, http://www.emulex.com/products/legacy/vi/clan1000.html
  8. ftp://ftp.compaq.com/pub/supportinformation/papers/tc000602wp.pdf
  9. N. J Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J N. Seizovic, W. Su, 'Myrinet- A Gigabit per second Local Area Network,' IEEE Micro, 1995 https://doi.org/10.1109/40.342015
  10. IEEE Standard for Scalable Coherent Interface, IEEE Std 1596-1992, IEEE Computer Society, Aug. 1993
  11. Jeonghec Shin, Sang-Hwa Chung, Woojong Hahn, 'An SCI-based Software VIA System for PC Clustering,' 2001 IEEE International Conference on Cluster Computing, Newport Beach, USA, Oct. 2001 https://doi.org/10.1109/CLUSTR.2001.959982
  12. M. Banikazemi, J. Liu, S. Kutlug, A. Ramakrishna, P. Sadayappan, H. Sah, and D. K. Panda, 'VIBe: A Micro-benchmark Suite for Evaluating Virtual Interface Architecture (VIA) Implementations,' Int'l Parallel and Distributed Processing Symposium (IPDPS), April 2001 https://doi.org/10.1109/IPDPS.2001.924960
  13. Mark Baker, Paul A. Farrell, Hong Ong, Stephen 1. Scott, 'VIA Communication Performance on a Gigabit Ethernet Cluster,' Euro-Par 2001, 132-141
  14. Hon Ong, Paul A. Farrell 'Performance Comparison of LAM/MPI, MPICH, and MVICH on a Linux Cluster connected by a Gigabit Ethernet Network,' Proc. of 4th Annual Linux Showcase & Conference, 2000
  15. In-Su Yoon, Sang-Hwa Chung, Ben Lee, and Hyuk-Chul Kwon, 'Implementation and Performance Evaluation of M -VIA on AceNIC Gigabit Ethernet Card,' Proc. Of the Euro-Par 2003, August 2003
  16. M. Banikaze, B. Abali, and D. K. Panda, 'Comparison and Evaluation of Design Choices for Implementing the Virtual Interface Architecture (VIA),' Fourth Int'l Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC '00), Jan 2000 https://doi.org/10.1007/10720115_11