대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

l0b 150 MSample/s 1.8V 123 mW CMOS 파이프라인 A/D 변환기

A l0b 150 MSample/s 1.8V 123 mW CMOS A/D Converter

  • 발행 : 2004.01.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 샘플링 주파수보다 더 높은 입력 대역폭을 얻기 위해서 개선된 부트스트래핑 기법을 적용한 l0b 150 MSample/s A/D를 제안한다. 제안하는 ADC는 다단 파이프라인 구조를 사용하였고, MDAC의 캐패시터 수를 $50\%$로 줄이는 병합 캐패시터 스위칭 기법을 적용하였으며, 저항 및 캐패시턴스의 부하를 고속에서 구동할 수 있는 기준 전류/전압 발생기와 고속 측정이 용이한 decimator를 온-칩으로 구현하였다. 제안하는 ADC 시제품은 0.18 um IP6M CMOS 공정을 이용하여 설계 및 제작되었고, 시제품 ADC의 측정된 DNL과 INL은 각각 $-0.56{\~}+0.69$ LSB, $-1.50{\~}+0.68$ LSB 수준을 보여준다. 또한, 시제품 측정결과 150 MSample/s 샘플링 주파수에서 52 dB의 SNDR을 얻을 수 있었고, 입/출력단의 패드를 제외한 시제품 칩 면적은 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm)이며, 최대 동작 주파수인 150 MHz에서 측정된 전력 소모는 123 mW이다.

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

키워드

참고문헌

  1. H. Marie and P. Belin, 'R, G, B acquisition interface with line-locked clock generator for flat panel display,' IEEE J. Solid-State Circuits, vol. 33, pp. 1009-1023, July 1998 https://doi.org/10.1109/4.701244
  2. H. Pleog, G. Hoogzaad, H. Temeer, M. Vertregt, and R. Roovers, 'A 2.5V 12b 54MSample/s 0.25um CMOS ADC in 1mm2,' in ISSCC Dig. Tech Papers, Feb. 2001, pp. 132-133
  3. A. Shabra and H. S. Lee, 'A 12-bit mismatch-shaped pipeline A/D converter,' in Symp. VLSI Circuits Dig. Tech Papers, June 2001, pp. 211-214 https://doi.org/10.1109/VLSIC.2001.934242
  4. L. Singer, S. Ho, M. Timko, and D. Kelly, 'A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz,' in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 38-39 https://doi.org/10.1109/ISSCC.2000.839681
  5. H. Pan, M. Segami, M. choi, J. Cao, F. Halorl, and A. A. Abidi, 'A 3.3V 12b 50MSample/s A/D converter in 0.6um CMOS with over 80dB SFDR,' in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 40-41
  6. B. Murmann, and B. E. BoserTsay, 'A 12b 75MS/s pipelined ADC using open-loop residue amplification,' in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 328-329 https://doi.org/10.1109/ISSCC.2003.1234320
  7. B. M. Min, P. Kim, D. Boisvert, and A. Aude, 'A 69mW 10b 80MS/s pipelined CMOS ADC,' in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 324-325 https://doi.org/10.1109/ISSCC.2003.1234318
  8. M. Clara, A. Wiesbauer, F. Kuttner, 'A 1.8V fully embedded 10b 160MS/s two-step ADC in 0.18um CMOS,' in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp. 437-440
  9. S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, 'A 2.5V 10b 120Msample/s CMOS pipelined ADC with high SFDR,' in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp. 441-444
  10. M. J. Kim, H. S. Yoon, Y. J. Lee, and S. H. Lee, 'An 11b 70MHz $1.2mm^2$ 49mW 0.18um CMOS ADC with on-chip current/voltage references,' in Proc. Eur. Solid-State Circuits Conf., Sep. 2002, pp. 463-466
  11. A. Loloee, A. Zanchi, H. Jin, S. Shehata, and E. Bartolome, 'A 12b 80MSps pipelined ADC core with 190mW consumption from 3V in 0.18um digital CMOS,' in Proc. Eur. Solid-State Circuits Conf., Sep. 2002, pp. 467-470
  12. S. Andreas, H. E. Bernhard, P. E. Herbert, R. Hagelauer, and A. A. Abidi, 'A 1.2V 10-b 100MSamples/s A/D converter in 0.12um CMOS,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2002, pp. 326-327
  13. D. Kelly, W. Yang, L. Mehr, M. Sayuk, and L. Singer, 'A 3V 340mW 14b 75MSPS ADC with 85dB SFDR at nyquist,' in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 134-135
  14. Y. I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, 'A 10b 100MSample/s CMOS pipelined ADC with 1.8V power supply,' in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 130-131
  15. L. Sumanen, M. Waltari, and K. Halonen, 'A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,' IEEE J. Solid-State Circuits, vol. 36, pp. 1048-1055, July 2001 https://doi.org/10.1109/4.933460
  16. D. G. Nairn, 'A 10-b, 3V, l00MS/s pipelined ADC,' in Proc. IEEE Custom Integrated Circuits Conf., May 2000, pp. 257-260
  17. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, 'A 10-b l00MS/s CMOS A/D converter,' in Proc. IEEE Custom Integrated Circuits Conf., May 1996, pp. 419-422
  18. S. M. Jamal, D. Fu, P. J. Hurst, and S. H. Lewis, 'A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration,' in ISSCC Dig. Tech. Paper, Feb. 2002, pp. 172-173 https://doi.org/10.1109/ISSCC.2002.992991
  19. A. M. Abo and P. R. Gray, 'A l.5-V, 10-bit, 14.3-MS/s CMOS pipelined analog-to-digital converter,' IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999 https://doi.org/10.1109/4.760369