References
- Bakoglu, H.B., Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, 1990
- Burstein, M., Pelavin, R., 'Hierarchical Wire Routing,' IEEE Trans. on CAD., Vol. CAD-2, No. 4, pp. 223-234, 1983 https://doi.org/10.1109/TCAD.1983.1270040
- Chen, Z. and Koren, I., 'Crosstalk Minimization in Three-Layer HVH Channel Routing,' IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 38-42, Oct. 1997 https://doi.org/10.1109/DFTVS.1997.628307
- Chen, H.H. and Wong, C.K., 'Wiring and Crosstalk Avoidance in Multi-chip Module Design,' Proc. Custom-Integrated Circuits Conf., pp. 28.6.1-28.6.4, May 1992
- Deutsch, D.N., 'A Dogleg Channel Router,' Proc. Design Automation Conf., pp. 425-433, Jun. 1976 https://doi.org/10.1145/800146.804843
- Gao, T. and Liu, C.L., 'Minimum Crosstalk Channel Routing,' IEEE Trans. Computer-Aided Design, Vol. 15, No. 5, May. 1996 https://doi.org/10.1109/43.506134
- Gao, T. and Liu, C.L., 'Minimum Crosstalk Switchbox Routing,' Proc. Int. Conf. Computer Aided Design, pp. 610-615, 1994
- Jhang, K.S., Ha, S. and Jhon, C.S., 'COP : A Crosstalk Optimizer for Gridded Channel Routing,' IEEE Trans. Computer-Aided Design, Vol. 15, No. 4, pp. 424-429, Apr. 1996 https://doi.org/10.1109/43.494705
- LP Solve, ftp://ftp.ics.ele.tue.nl
- MOSIS, http://www.mosis.org
- Ohtsuki, T., Layout Design and Verification, North-Holland, 1986
- Onozawa, A., Chaudhary, K. and Kuh, E.S., 'Performance Driven Spacing Algorithms Using Attractive and Repulsive Constraints for Submicron LSI's,' IEEE Trans. Computer- Aided Design, Vol. 14, No. 6, pp. 707-719, Jun. 1995 https://doi.org/10.1109/43.387731
- Parakh, P.N. and Brown, R.B., 'Crosstalk Constrained Global Route Embedding,' Proc. Int. Symp. Physical Design, pp. 201-206, Apr. 1999 https://doi.org/10.1145/299996.300077
- Sakurai, T. and Tamaru, K., 'Simple Formulas for Two-and Three-Dimensional Capacitances,' IEEE Trans. Electron Devices, Vol. ED-30, No. 2, pp. 183-185, Feb. 1983 https://doi.org/10.1109/T-ED.1983.21093
- Saxena, P. and Liu, C.L., 'A Postprocessing Algorithm for Crosstalk-Driven Wire Perturbation,' IEEE Trans. Computer-Aided Design, Vol. 19, No. 6, pp. 691-702, Jun. 2000 https://doi.org/10.1109/43.848090
- Thakur, S., Chao, K.Y. and Wong, D.F., 'An Optimal Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing,' Proc. IEEE Intl. Symp. on Circuits and Systems, pp. 207-210, 1995
- Vittal, A. and Marek-Sadowska, M., 'Crosstalk Reduction for VLSI,' IEEE Trans. Computer Aided Design, Vol. 16, No. 3, pp. 290-298, Mar. 1997 https://doi.org/10.1109/43.594834
- Wang, D. and Kuh, E.S., 'A Performance driven MCM Router with Special Consideration of Crosstalk Reduction,' Proc. Design Automation and Test in Europe, pp. 466-470, 1998 https://doi.org/10.1109/DATE.1998.655899
- Xue, T. Huh, E.S. and Wang, D., 'Post Global Routing Corsstalk Synthesis,' IEEE Trans. Computer-Aided Design, Vol. 16, No. 12, pp. 1418-1430, Dec. 1997 https://doi.org/10.1109/43.664224
- Yoshimura, T. and Kuh, E.S., 'Efficient Algorithms for Channel Routing,' IEEE Trans. Computer-Aided Design, Vol. CAD-1, No. 1, pp. 25-35, Jan. 1982 https://doi.org/10.1109/TCAD.1982.1269993
- Zhou, H. and Wong, D.F., 'Crosstalk Constrained Maze Routing Based on Lagrangian Relaxation,' Proc. Int. Conf. Computer Design, pp. 628-633, 1997 https://doi.org/10.1109/ICCD.1997.628931
- Zhou, H. and Wong, D.F., 'Global Routing with Crosstalk Constraints,' IEEE Trans. Computer-Aided Design, Vol. 18, No. 11, pp. 1683-1688, Nov. 1999 https://doi.org/10.1109/43.806813