대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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저 전력소모와 높은 테스트용이성을 위한 새로운 논리 변환 방법

A New Logic Transformation Method for Both Low Power and High Testability

  • 발행 : 2003.09.01
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초록

본 논문에서는 저 전력소모와 높은 테스트용이성을 동시에 고려하기 위한 새로운 게이트 레벨 논리변환 방법을 제안한다. 주출력에서 관측될 확률이 낮은 CFF(Compact Fanout Free)를 찾아내고, 해당 CFF가 모든 주출력에서 관측불가능한 조건에서는 리던던트 연결을 첨가하여 내부에서 발생하는 스위칭 동작을 제거한다. 일반적으로 논리 변환된 회로의 테스트 용이성은 떨어지는 경향이 있다. 그러나 제안된 방법에서 첨가된 리던던트 연결은 테스트 모드에서 테스트 포인트로 동작하며 CFF의 제어도와 관측도를 동시에 향상시키게 된다. 따라서 논리 변환된 회로는 정상 모드에서는 전력 손실이 매우 낮으며, 테스트 모드에서는 높은 테스트용이성을 갖는다. 제안하는 논리 변환 방법의 효율성을 보이기 위하여 MCNC 벤치마크 테스트 회로에 대하여 실험을 수행하였다. 실험 결과로부터 변환된 회로의 전력소모는 최대 13%정도 감소하며, 고장 검출율은 오히려 증가함을 확인할 수 있다.

In this paper, a new logic transformation method to consider both low power consumption and high testability is proposed. We search the CFF(Compact Fanout Free) that has low probability of being observable at the primary outputs. Under the condition that the CFF is unobservable at all primary outputs, the switching operations in it can be removed by adding redundant connections into it. The testability of the transformed circuit generally tends to reduce. In our method, however, the inserted redundant connections operate as test points in the test mode and can improve not only the controllability but also the observability of the CFF. The transformed circuit consumes less power in the normal mode and also has higher testability in the test mode. To show the efficiency of the proposed logic transformation method, we perform some experiments on the MCNC benchmark test circuits. The results show that the power consumption of the transformed circuit is reduced by 13% maximally and the fault coverage of the transformed circuit is increased.

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참고문헌

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