변형된 레지스터 교환 방식의 비터비 디코더 설계

Design of Viterbi Decoders Using a Modified Register Exchange Method

  • 이찬호 (숭실대학교 정보통신전자공학부) ;
  • 노승효 (삼성전자 시스템 LSI 사업부 LSI 개발 1팀)
  • 발행 : 2003.01.01

초록

본 논문에서는 비터비 디코더의 디코딩과정에서 trace-forward 과정이후. trace-back 동작 없이 decision bit를 결정 가능한 구조로 설계하여 사용 메모리 크기와 동작 cycle에서 이득을 가지는 변형된 레지스터 교환(modified register exchange) 방식을 제안하였다. 제안된 구조는 시뮬레이션에 의해 trace-back이 있는 기존의 방식과 동일한 결과를 나타냄을 확인하였으며, 변형된 레지스터 교환 방식과 기존의 레지스터 교환 방식, 그리고 trace-back 방식과 비교하였다. 제안한 방식은 다른 방식들에 비해 메모리를 1/(5 x constraint length)로 줄일 수 있고, trace-back 방식에 비해 throughput을 2배 향상시켰다. 변형된 레지스터 교환 방식을 적용한 비터비 디코더의 동작을 검증하기 위해 code rate 2/,3, constraint length, K가 3인 디코더를 radix-4 구조의 1 bit 디코딩 방식으로 설계하여 FPGA(field programmable gate away)를 이용하여 구현하고 측정을 통해 오류 정정 작용을 확인하였다. 또한 블록 디코딩 방식에도 적용할 수 있음을 보였다.

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K=3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

키워드

참고문헌

  1. Peter Sweeney, Error Control Coding an introduction, Prentice Hall, 1991
  2. Shu Lin, Daniel J. Costello, Jr, Error Control Coding: Fundamentals and Applications, Prentice Hall, 1983
  3. Feygin, G., Chow, P., Gulak, P.G., Chappel, J., Goodes, G., Hall, O., Sayes, A., Singh, S., Smith, M.B., Wilton, S., 'A VLSI implementation of a cascade Viterbi decoder with traceback', Circuits and Systems. 1993., ISCAS '93. 1993 IEEE International Symposium on, May 1993 Page(s): 1945-1948 Vol. 3 https://doi.org/10.1109/ISCAS.1993.394131
  4. Jens Sparso, Henrik N. Jorgensen, Erik Paaske, Steen Pedersen, Thomas Rubner-Petersen, 'An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures', IEEE J. Solid-State Circuits, Vol. 26, No. 2, pp. 90-97, FEBRUARY 1991 https://doi.org/10.1109/4.68122
  5. Montse Boo, Francisco Arguello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata, 'High-Performance VLSI Architecture for the Viterbi Algorithm', IEEE Trans. Communication, Vol. 45, pp. 168-176, FEBRUARY 1997 https://doi.org/10.1109/26.554365
  6. Peter J. Black, Teresa H. Meng, 'A 140-Mb/s 32-state, Radix-4 Viterbi Decoder' IEEE J. Solid-State Circuits, Vol. 27, pp. 1877-1885, DECEMBER 1992 https://doi.org/10.1109/4.173118
  7. K. Hu, W. Lin, M. Caldwell, 'A Viterbi Decoder Memory Management System Using Forward Traceback and All-Path Traceback' Proceedings of the IEEE 1999 International Conference on Consumer Electronic, pp. 68-99 https://doi.org/10.1109/ICCE.1999.785171
  8. Peter J. Black and Teresa H.-Y. Meng, 'A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder', IEEE J. Solid-State Circuits, Vol 32, No. 6, pp. 797-805, JUNE 1997 https://doi.org/10.1109/4.585246
  9. Mansoor A. Chirstie, 'Viterbi Implementation on the TMS320C5x for V.32 Modems, Digital Signal Processing Applications-Semiconductor Group, Document #SPRA099.pdf, Texas Instruments Incorporated, Texas, 1996
  10. A. Mark Earnshaw, Steven D. Blostein, 'A Combined Soft-Decision Deinterleaver/Decoder for the IS95 Reverse Link', IEEE Trans. Vehicular Technology, Vol. 49, No. 2, pp. 448-452, March 2000 https://doi.org/10.1109/25.832976
  11. Vijay K. Garg, IS-95 CDMA and cdma2000 : Cellualar/PCS Systems Implementation, Prentice Hall, 2000
  12. Digital Signal Processing Applications-Semiconductor Group, Document #SPRA099.pdf Viterbi Implementation on the TMS320C5x for V.32 Modems Mansoor A. Chirstie
  13. IEEE Trans. Vehicular Technology v.49 no.2 A Combined Soft-Decision Deinterleaver/Decoder for the IS95 Reverse Link A. Mark Earnshaw;Steven D. Blostein https://doi.org/10.1109/25.832976
  14. IS-95 CDMA and cdma2000: Cellualar/PCS Systems Implementation Vijay K. Garg