Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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New DSP Instructions and their Hardware Architecture for the Viterbi Decoding Algorithm

비터비 복호 알고리즘 처리를 위한 DSP 명령어 및 하드웨어 회로

  • Published : 2002.11.01
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Abstract

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

본 논문은 비터비 복호(Decoding)를 DSP(Digital Signal Processor)에서 효율적이고 빠르게 구현 할 수 있는 명령어 집합 및 하드웨어 회로를 제안한다. 제안하는 하드웨어 구조는 기존의 DSP 칩에 비터비 복호 알고리즘의 연산 구조에 효율적인 명령어 및 이에 가장 적합한 연산 유닛의 배열과 데이터 패스 구조를 추가하여 비터비 복호뿐만 아니라 일반 신호 처리 알고리즘들을 구현 할 수 있다. 기존의 DSP 칩이 수십 Kbps 대의 전송률에서 비터비 복호를 수행하는 반면 본 구조는 100MHz 동작 주파수를 갖는 DSP 칩에서 6.25 Mbps의 전송률의 비터비 복호를 수행할 수 있어 전용 비터비 프로세서에 근접한 성능을 갖는다. 따라서 본 구조는 IMT-2000의 요구 전송률인 2Mbps 환경에서도 사용 가능하다.

Keywords

References

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